Ceramic substrate for three-dimensional packaging of multi-chip system and packaging method thereof

A technology of ceramic substrate and three-dimensional packaging, applied in the field of ceramic substrate

Active Publication Date: 2010-05-26
MEMSIC SEMICON WUXI
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Two-dimensional planar chip surface mount technology (SMT) has been very mature, but thre

Method used

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  • Ceramic substrate for three-dimensional packaging of multi-chip system and packaging method thereof
  • Ceramic substrate for three-dimensional packaging of multi-chip system and packaging method thereof
  • Ceramic substrate for three-dimensional packaging of multi-chip system and packaging method thereof

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Experimental program
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Embodiment Construction

[0040] In order to further understand the purpose of the present invention, the packaging structure and its features, the detailed description is as follows in conjunction with the accompanying drawings:

[0041] A ceramic substrate for three-dimensional packaging of a multi-chip system according to the present invention includes a laminated ceramic 6, a first cavity 2 is formed in the horizontal plane of the laminated ceramic 6 to accommodate the first chip, and the first cavity A cover plate 1 is arranged above the body 2, and the cover plate 1 seals the first cavity 2 and the first chip 4. It is characterized in that: the side wall of the laminated ceramic 6 has a The second cavity 3 of a cavity 2 is to accommodate the second chip 9, and a pad interconnected with the second chip is arranged in the second cavity 3, and the pad is electrically connected to the first cavity. interconnection. The cover plate seals the first cavity 2 and the first chip 4 through a sealing membe...

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Abstract

The invention discloses a ceramic substrate for three-dimensional packaging of a multi-chip system, which comprises laminated ceramic, wherein a first cavity for containing a first chip is formed in a horizontal plane of the laminated ceramic; a cover plate is arranged above the first cavity and seals the first cavity and the first chip; a second cavity for containing a second chip, which is vertical to the first cavity, is arranged on the side wall of the laminated ceramic; and a bonding pad interconnected with the second chip is arranged in the second cavity and is electrically interconnected with the first cavity. The invention can provide hermetic packaging for a multi-chip module and simultaneously can provide vertical surface attaching for chips, thereby realizing vertical attaching of IC chips or MEMS chips, forming a three-dimensional packaged system module with high reliability, and enabling the chips to be capable of detecting variations of physical quantities in X, Y and Z directions.

Description

technical field [0001] The invention relates to a ceramic substrate used for three-dimensional packaging of a multi-chip component system, and also relates to a method for three-dimensional packaging of a multi-chip system by using the ceramic substrate. Background technique [0002] With the progress of integrated circuit technology and the rapid development of new electronic packaging technology, conditions have been created for the improvement of the performance of electronic products, the enrichment and perfection of functions, and the reduction of costs. Microelectronics packaging has experienced dual in-line (DIP) packaging, quad flat (QPF) packaging, ball array packaging (BGA) and chip size (CSP) packaging, etc., the size is getting smaller and smaller, and electronic devices are also composed of discrete devices, Integrated circuits, System-on-Chip (SOC), and more complex System-in-Package (SIP). SIP uses micro-assembly and interconnection technology to integrate va...

Claims

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Application Information

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IPC IPC(8): H01L25/065H01L21/50H01L21/52B81C99/00
CPCH01L24/97H01L2224/05554H01L2224/48091H01L2224/48227H01L2924/14
Inventor 朱大鹏
Owner MEMSIC SEMICON WUXI
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