Lateral diffused metal oxide semiconductor transistor structure capable of avoiding double-hump effect

An oxide semiconductor and transistor technology, applied in semiconductor devices, electrical components, circuits, etc., can solve the problems of transistor leakage, low turn-on voltage, low turn-on voltage, etc., and achieve the effect of constant threshold voltage Vt and uniform thickness

Active Publication Date: 2010-06-02
SHANGHAI HUAHONG GRACE SEMICON MFG CORP
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Problems solved by technology

[0006] In the above mechanism, the thinner part of the oxide layer GOX is the effective conductive part, and because this part of the oxide layer GOX is relatively thin, it can withstand a lower turn-on voltage, which in turn causes the LDNMOS to have a lower turn-on voltage. This turn-on The voltage is lower than the normal turn-on voltage of the transistor, thus forming two bumps on the Id-Vg

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  • Lateral diffused metal oxide semiconductor transistor structure capable of avoiding double-hump effect
  • Lateral diffused metal oxide semiconductor transistor structure capable of avoiding double-hump effect
  • Lateral diffused metal oxide semiconductor transistor structure capable of avoiding double-hump effect

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[0021] In order to better understand the technical content of the present invention, specific embodiments are given and described below in conjunction with the accompanying drawings.

[0022] Figure 4 is a schematic top view of the LDNMOS structure disclosed in the present invention; Figure 5 for Figure 4 The cross-sectional schematic diagram of the LDNMOS structure along the x direction; Image 6 for Figure 4 A schematic cross-sectional view of the LDNMOS structure along the y-direction.

[0023] Please also refer to Figures 4 to 6 , In this embodiment, the LDNMOS structure includes a base layer B, an oxide layer GOX, and a polysilicon layer P sequentially from bottom to top.

[0024] In this embodiment, the base layer B is an N well, and the polysilicon layer P formed thereon serves as the gate G of the LDNMOS. There are correspondingly arranged N-type drift regions N-d on both sides of the oxide layer GOX in the base layer B as the source S and the drain D of the...

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Abstract

The invention provides a lateral diffused metal oxide semiconductor transistor structure which comprises a substrate layer, an oxidation layer and a polysilicon layer which are distributed from bottom to top, wherein the polysilicon layer is used as a gate electrode of the LDNMOS; two N type drift regions are respectively positioned at two sides of the oxidation layer in the substrate layer for being used as a source electrode and a drain electrode of the LDNMOS; a P type drift region is annularly arranged outside the gate electrode, the source electrode and the drain electrode of the LDNMOS in the substrate layer for being used as a base electrode of the LDNMOS; and the distance between each of the edges at the other two sides of the oxidation layer and the edge of the P type drift region is 0-0.2mu m. The LDNMOS structure provided by the invention enables the thinner part in the gate oxide (GOX) of the LDNMOS to be positioned outside the N type drift regions and beyond the effectivesize range of the device, and the effective gate oxide thickness is kept uniform to prevent the MOS from being opened at lower subthreshold voltage caused by the thinner gate oxide, thereby limiting the double-hump effect of the LDNMOS.

Description

technical field [0001] The invention relates to a structure of a laterally diffused metal oxide semiconductor transistor, and further relates to a structure of a laterally diffused metal oxide semiconductor transistor which avoids the double peak effect. Background technique [0002] Laterally Diffused N type Metal Oxidesemiconductor (LDNMOS) plays an important role in the design and manufacture of several circuits. For example, a laterally diffused metal oxide semiconductor transistor (HV LDNMOS) is widely used in a driver chip of a thin film transistor liquid crystal display. [0003] The structure diagram of the current LDNMOS is as follows figure 1 and figure 2 as shown, figure 1 is a schematic top view of a known LDNMOS structure; figure 2 for figure 1 Schematic diagram of the cross-section of the LDNMOS along the x direction; image 3 for figure 1 Schematic diagram of the cross-section of the LDNMOS along the y direction. The LDNMOS includes a base layer B, a...

Claims

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Application Information

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IPC IPC(8): H01L29/78H01L29/06
Inventor 刘龙平令海阳陈爱军易亮黄庆丰杨华岳
Owner SHANGHAI HUAHONG GRACE SEMICON MFG CORP
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