Method for manufacturing alignment mark of semiconductor silicon wafer and semiconductor silicon wafer thereby

Abstract

The invention discloses a method for manufacturing an alignment mark of a semiconductor silicon wafer. The method comprises the following steps of: depositing a layer of luminescent material on the back face of the semiconductor wafer, photoetching the back of the semiconductor wafer, manufacturing the alignment mark through corrosion and removing photoresist. The invention also discloses a semiconductor wafer, the back of the semiconductor wafer is provided with the alignment mark which is made of the luminescent material. In the invention, the alignment mark is arranged on the back of the semiconductor wafer, thereby the use area of the front of the wafer is greatly saved. The position of the alignment mark is fixed so that an alignment signal can not be influenced by different products and different processes.

Description

technical field [0001] The invention relates to a method for manufacturing an alignment mark of a semiconductor silicon wafer. The invention also relates to a semiconductor silicon wafer. Background technique [0002] Currently, in semiconductor manufacturing, alignment marks are placed in the dicing lanes on the front side of the silicon wafer, thus reducing the area used on the front side of the silicon wafer. Especially in the development of a new process, it is often necessary to add many batches of alignment marks for evaluation. At this time, the dicing lanes are often not enough. Simultaneously, because the chip size of the silicon chip of the new product that develops every time is different, need rearrange the position of alignment mark every time; profile) and signal strength will be affected. [0003] In addition, in various processes of semiconductors, the morphology of the alignment marks may change due to various reasons. Such as figure 1 As shown, when th...

AI Technical Summary

Problems solved by technology

Especially in the development of new processes, it is often necessary to add many batches of alignment marks for evaluation. At this time, the dicing lanes are often not enough

Simultaneously, because the chip size of the silicon chip of the new product that develops every time is different, need rearrange the position of alignment mark every time; profile) and signal strength will be affected

[0003] In addition, in various processes of semiconductors, the morphology of alignment marks may change due to various reasons

like figure 1 As shown, when the shape of the alignment mark changes, a secondary peak may be introduced, resulting in distortion of the alignment signal, thereby affecting the coordinates of the alignment mark

Images