Quad flat no-lead encapsulation structure and encapsulation method thereof

Abstract

The invention provides an encapsulation method of a quad flat no-lead encapsulation structure. The encapsulation method comprises the following steps: providing a flat film with a viscous surface; adhering a chip base and a lead frame which are used for encapsulating a chip to the viscous surface of the film; performing injection molding on the chip base and the lead frame by using a first injection mould and insulation adhesive; removing the film, the first injection mould and the insulation adhesive; adhering the chip to the exposed surface of the chip base by using conductive adhesive; electrically connecting pads on the surface of the chip with a base pin of the lead frame; and performing injection molding by using a second injection mould and the insulation adhesive. The invention further provides the quad flat no-lead encapsulation structure obtained by the method of the invention. The invention has the advantage that the chip base can be ensured to be completely covered by the insulation adhesive and can not be exposed in the follow-up processes, thus increasing the insulation property between pads.

Description

【Technical field】 [0001] The invention relates to the field of semiconductor packaging, in particular to a quadrilateral flat leadless packaging structure and a packaging method thereof. 【Background technique】 [0002] With the rapid development of electronic manufacturing technology, consumer electronic products are becoming more and more small and portable, which also leads to an increasingly limited space for arranging electrical components inside these electronic products. In this case, the electrical components used must be as thin as possible, which has become the current development trend of electronic component manufacturing. The quad flat no-leads (QFN) process can just meet this demand. [0003] attached figure 1 Shown is a schematic cross-sectional view of a typical QFN package structure in the prior art, including a chip 900 , a heat sink 920 , a lead frame 930 , multiple wires 940 , and insulating glue 950 wrapping the above structure. The chip 900 is adhered...

AI Technical Summary

Problems solved by technology

[0005] In the prior art, although the heat sink in the packaging structure of the QFN package is conducive to the heat dissipation of the chip to the outside during the working process, it leads to the deterioration of the insulation properties between the conductive pins of the package.

For chips with low heat generation, users often prefer good insulation performance between the conductive pins of the package. seems redundant

For the current QFN process, the bottom of the package must have an exposed conductive heat sink, which limits the application field of the QFN packaging process.

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