GGNMOS (grounded-gate negative-channel metal oxide semiconductor) device and making method thereof

A manufacturing method and device technology, applied in the direction of semiconductor/solid-state device manufacturing, semiconductor devices, electrical components, etc., can solve problems such as affecting ESD discharge capability, reducing the slope of the conduction curve, and increasing the device area to improve the triggering effect. , The effect of saving chip area and reducing the concentration of P well

Active Publication Date: 2010-06-16
SHANGHAI HUAHONG GRACE SEMICON MFG CORP
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  • Abstract
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Problems solved by technology

However, an excessively long drain length not only increases the device area, but also redu

Method used

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  • GGNMOS (grounded-gate negative-channel metal oxide semiconductor) device and making method thereof
  • GGNMOS (grounded-gate negative-channel metal oxide semiconductor) device and making method thereof
  • GGNMOS (grounded-gate negative-channel metal oxide semiconductor) device and making method thereof

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[0030] The manufacturing method of the GGNMOS device of the present invention includes the following steps:

[0031] Step 1, see Figure 1a . An ion implantation process is used to implant N-type impurities on the P-type silicon substrate 10 to form a deep N-well 11. Commonly used N-type impurities are phosphorus, arsenic and antimony. High-temperature furnace annealing is used after ion implantation.

[0032] For example, the dosage of ion implanted phosphorus is 5×10 12 ions / cm 2 (Ion per square centimeter)~1.5×10 13 ions / cm 2 , The injection energy is 1000keV~2000keV. The annealing temperature in the high-temperature furnace is 1100°C to 1200°C, and the time is 1 to 3 hours.

[0033] Step 2, see Figure 1b . P-type impurities are implanted on the P-type silicon substrate 10 using an ion implantation process, and the range of ion implantation is all silicon above the deep N-well 11, so that the P-well 12 is formed on the deep N-well 11. Commonly used P-type impurities are boro...

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Abstract

The invention discloses a GGNMOS (grounded-gate negative-channel metal oxide semiconductor) device in a deep N-well. Under the condition that all dimensions of the device do not change, channel resistance can be obviously increased to realize that GGNMOS is triggered well; and the device is kept in a small dimension range for saving the area of a chip. The invention has the core of putting the GGNMOS device into the deep N-well rather than making a traditional GGNMOS device on a P-shaped substrate and has the advantages of compensating partial boron atoms of a P-well by the external diffusion of phosphorus atoms of the deep N-well, reducing the effective concentration of the P-well, increasing the channel resistance, improving the triggering effect of the GGNMOS, reducing the flowing cross-sectional area of source leakage current because the P-well and the P-well substrate are isolated by the deep N-well, and further increasing the channel resistance.

Description

technical field [0001] The invention relates to a semiconductor integrated circuit device, in particular to a MOS device. [0002] semiconductor manufacturing Background technique [0003] GGNMOS (gate-grounded NMOS, Gate-Grounded NMOS) is a basic element of an ESD (Electrostatic Discharge) circuit, and its electrostatic discharge capability determines the performance of an ESD circuit. The conventional GGNMOS process is formed by modifying the device structure on the basis of I / O NMOS, such as appropriately increasing the channel length, increasing the length of the drain terminal, and increasing ESD ion implantation, etc., in order to appropriately reduce the trigger voltage (Vt1, also known as primary breakdown voltage), adjust the sustain voltage (Vsp) and the slope of the conduction curve, and adjust the secondary breakdown voltage (Vt2) to be slightly greater than the trigger voltage. In order to effectively trigger the ESD device, in addition to reducing the trigger...

Claims

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Application Information

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IPC IPC(8): H01L29/78H01L21/336
Inventor 钱文生
Owner SHANGHAI HUAHONG GRACE SEMICON MFG CORP
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