Method for manufacturing memory

Abstract

The invention discloses a method for manufacturing a memory, which comprises the following steps: forming a common source area, a common drain area and a bottom dielectric layer on a semiconductor substrate; sequentially stacking a floating gate, an insulating layer and a control gate on the bottom dielectric layer; depositing a nitride on the upper surface and lateral surfaces of the gate structure formed by stacking the floating gate, the insulating layer and the control gate; depositing an oxide on the surface of the nitride to fill up the gap formed in the gate structure above the common source area; removing part of the oxide; and removing the nitride above the common drain area. In the method, the layer of oxide is deposited after the nitride is deposited, a function of delaying etching is realized in the nitride removing process and Co ions are prevented from entering the bottom dielectric layer above the common source area in a subsequent Co ion injection process, so the charges in the floating gate is prevented from escaping to the bottom dielectric layer above the common source area, the holding capacity of the data stored in the floating gate is improved, and the memory data storage time is improved.

Description

technical field [0001] The present invention relates to the field of semiconductor manufacturing methods, in particular to a memory manufacturing method. Background technique [0002] Memory is used to store a large amount of digital information, and according to recent surveys, the transaction volume of memory chips accounts for about 30% of the transaction volume of semiconductor chips worldwide. Over the years, the advancement of process technology and the increase of market demand have spawned many types of high-density memory chips, such as random access memory (RAM), dynamic random access memory (DRAM), read-only memory (ROM), erasable and programmable Read memory (EPROM), flash memory (FLASH) and ferroelectric memory (FRAM), etc. [0003] At present, the memory technology is developing in the direction of increasing the integration level and reducing the size of the components. When users use the memory, in addition to requiring the memory to have high storage capac...

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Problems solved by technology

[0011] When the data retention capability test is performed on the floating gate 5 of the memory made by the above-mentioned manufacturing process, the defect rate is more than 6%. When the nitride 8 on the upper surface of the region covering the common drain region 2 is removed, the nitride 8 on the upper surface of the region covering the common source region 3 in the bottom dielectric layer 4 will also be removed, resulting in subsequent implantation of Co ions. Co ions will also be implanted in the bottom dielectric layer 4 at the position of the region 3, and the subsequent chemical reaction steps make the bottom dielectric layer 4 at the position of the common source region 3 also contain cobalt disilicide 10

[0012] Therefore, during the data retention capability test of the floating gate 5, after the memory was baked for 24 hours, the testers found that the charges stored in the floating gate 5 would escape to the bottom dielectric containing cobalt disilicide 10 on the common source region 3 In layer 4, the data retention ability of the tested memory is poor, that is, the data storage time of the memory is reduced

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