Reducing power consumption during read operations in non-volatile storage
A non-volatile storage, non-volatile technology, applied in the field of non-volatile memory
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[0036] The present invention provides a method of reducing power consumption during a read operation in a non-volatile memory.
[0037] One example of a memory system suitable for implementing the invention uses a NAND flash memory structure that includes multiple transistors arranged in series between two select gates. Transistors and select gates connected in series are called NAND strings. figure 1 is a top view showing one NAND string. figure 2 is its equivalent circuit. figure 1 and 2The NAND string shown includes four transistors, 100 , 102 , 104 and 106 connected in series and sandwiched between a first select gate 120 and a second select gate 122 . Select gate 120 gates the connection of the NAND string to bit line 126 . Select gate 122 gates the connection of the NAND string to source line 128 . Select gate 120 is controlled by applying an appropriate voltage to control gate 120CG. Select gate 122 is controlled by applying an appropriate voltage to control gate...
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