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VDMOS and preparation method thereof

A manufacturing method and doping layer technology, which is applied in semiconductor/solid-state device manufacturing, electrical components, circuits, etc., can solve problems such as increasing device manufacturing costs, and achieve the effect of increasing manufacturing costs and reducing manufacturing costs

Active Publication Date: 2010-07-28
SEMICON MFG INT (SHANGHAI) CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

In the known VDMOS structure, the technology of buried drain region and epitaxial layer is adopted, which increases the manufacturing cost of the device

Method used

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  • VDMOS and preparation method thereof
  • VDMOS and preparation method thereof
  • VDMOS and preparation method thereof

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Experimental program
Comparison scheme
Effect test

no. 1 approach

[0016] refer to figure 2 , the present invention at first provides a kind of manufacturing method of VDMOS, comprises the steps:

[0017] Step S11, providing a semiconductor substrate;

[0018] Step S12, forming a doped layer on the base layer in the semiconductor substrate;

[0019] Step S13, forming a gate region on the doped layer; the gate region sequentially includes a gate oxide layer, a polysilicon layer, a silicide layer and sidewalls;

[0020] Step S14, forming isolation wells located on both sides of the gate region in the doped layer;

[0021] Step S15, forming a source region in the isolation well;

[0022] Step S16, forming an opening exposing the base layer in the doped layer;

[0023] Step S17, forming an isolation side wall in the opening;

[0024] Step S18, forming a drain region on the base layer along the opening;

[0025] Step S19, filling the opening with a conductive substance to form a conductive plug.

[0026] The above purpose and the advantage...

no. 2 approach

[0054] refer to Figure 12 , the present invention at first provides a kind of manufacturing method of VDMOS, comprises the steps:

[0055] Step S21, providing a semiconductor substrate;

[0056] Step S22, forming a doped layer on the base layer in the semiconductor substrate;

[0057] Step S23, forming an opening exposing the base layer in the doped layer;

[0058] Step S24, forming an isolation side wall in the opening;

[0059] Step S25, forming a drain region on the base layer along the opening;

[0060] Step S26 , filling the opening with a conductive substance to form a conductive plug.

[0061] Step S27, forming a gate region on the doped layer; the gate region sequentially includes a gate oxide layer, a polysilicon layer, a silicide layer and sidewalls;

[0062] Step S28, forming isolation wells located on both sides of the gate region in the doped layer;

[0063] Step S29, forming a source region in the isolation well;

[0064] first reference Figure 12 with ...

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Abstract

The invention relates to a VDMOS and a preparation method thereof. Wherein the VDMOS comprises a base layer and a doping layer in a semiconductor substrate, a gate region on the doping layer; wherein the base layer comprises a drain electrode region at the two sides of the gate region, the doping layer comprise a conductive plug adapter which is located on the drain electrode region and penetrates through the doping layer, an isolated well at the two sides of the gate region and a source electrode region located in the isolated well. In the invention, highly costly buried drain electrode region and extension layer technology is not needed, so that manufacturing cost is lowered.

Description

technical field [0001] The invention relates to the manufacturing field of semiconductor devices, in particular to a VDMOS and a manufacturing method thereof. Background technique [0002] Power Metal-Oxide-Semiconductor Field Effect Transistor (Power MOSFET) structure has a wide range of applications in a very wide range of fields due to its special functions, for example, disk drives, automotive electronics, and power devices. [0003] Taking the power device as an example, the output rectifier of the VLSI device applied to the power device is required to be able to output a voltage of about 3.3V when inputting a voltage of 20V and to output a voltage of about 1.5V when inputting a voltage of 10V; and the device is required to have Depletion voltage range from 10V to 50V. Some existing devices cannot meet the requirements, for example, the exhaustion voltage range of Schottky diodes is about 0.5V. [0004] VDMOS (Vertical double-diffused metal oxide semiconductor, vertic...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/336H01L21/265H01L21/31H01L29/78H01L29/08
Inventor 三重野文健季明华
Owner SEMICON MFG INT (SHANGHAI) CORP
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