Input buffer circuit for high-speed pipeline analog-to-digital converter

Abstract

The invention provides a input buffer circuit for high-speed pipeline analog-to-digital converter (ADC). The input buffer circuit comprises an input pair transistor, a current mirror load, a gain-boosted amplifier and a compensation capacitor, wherein the input pair transistor consists of a first MOS (metal oxide semi-conductor) transistor and a second MOS transistor of a source negative-feedback resistor; the current mirror load consists of a third MOS transistor and a fourth transistor which are connected to each other by a gate; the positive input terminal of the gain-boosted amplifier is connected with the drain of the first MOS transistor, the negative input terminal thereof is connected with the drain of the second MOS transistor, and the output terminal thereof is connected with the gate of the third MOS resistor; and one terminal of the compensation capacitor is connected with the gate of the third MOS transistor, and the other terminal thereof is connected with the drain of the third MOS transistor. The input buffer circuit of the invention is capable of meeting the requirements for the input of high-speed signals, effectively reducing the inputted load capacitance and increasing the outputted impedance.

Description

Technical field [0001] The invention relates to an integrated circuit used in the field of communication technology, and in particular to an input buffer circuit of a high-speed analog-to-digital converter. Background technique [0002] With the rapid development of the communications industry, various electronic devices are being widely used, such as mobile phones, computers, MP4 and so on. In these electronic devices, the analog-to-digital converter has become indispensable as an interface circuit for analog signals and digital signals, and its applications are increasing. In order to process video signals, the analog-to-digital converters used in some electronic devices require high speed, which puts higher requirements on the input bandwidth and linearity of the analog-to-digital converters. The usual approach is to make an ADC drive circuit outside the ADC chip. Such drive circuit is generally a closed-loop amplifier, but this not only requires an additional amplifier, but ...

AI Technical Summary

Problems solved by technology

[0008] However, the biggest disadvantage of circuit 100 and circuit 101 is that the gain is relatively low, because usually the gain of a common single-stage operational amplifier is below 40dB, and if the quiescent current is increased in order to meet the high-speed requirements, the gain will be lower, so in the closed loop In the system application, it will lead to a relatively large error in the input and output, which will reduce the spurious-free dynamic range (SFDR) of the input signal

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