asic chip verification method and programmable gate array

Abstract

The embodiment of the invention provides an ASIC (Application Specific Integrated Circuit) chip verification method and a programmable gate array, aiming to solve the problem of more I / O (Input / Output) pin resources occupied by an FPGA (Field Programmable Gate Array) chip-to-chip connection method or demand of reducing the interface rate between modules to be verified in the prior art. The method comprises the following steps of: packaging interface signals on first module interfaces to be verified into a first multiplexing data packet by a first multiplexing / demultiplexing module according to the quantity of the first module interfaces to be verified and sending the first multiplexing data packet to a first parallel / serial-serial / parallel conversion module; and converting the first multiplexing data packet into serial data by the first parallel / serial-serial / parallel conversion module and then sending. Compared with the prior art, the invention reduces the occupation of I / O pins in the FPGA, thereby simplifying work such as designing, PCB (Printed circuit board) wiring, and the like of an FPGA verification platform. In addition, the transmission rate of a parallel / serial-serial / parallel module interface (serdes) of the FPGA in the embodiment of the invention is high, and the invention is particularly suitable for scenes with higher interface rate between modules to be verified.

Description

technical field [0001] The invention relates to the field of chip design, in particular to an ASIC chip verification method and a programmable gate array. Background technique [0002] Application Specific Integrated Circuit (ASIC, Application Specific Integrated Circuit) prototype verification refers to the use of field programmable gate arrays (FPGA, Field Programmable Gate Array) for netlist-level functional verification and partial system verification during the ASIC development process. Due to the relatively large scale of the netlist, several FPGAs are generally used for interconnection with input / output (I / O, Input-Output) pins to form an FPGA array capable of carrying the netlist for internal logic of the netlist and external devices. Code-level debugging of interfaces. As the scale of the netlist becomes larger and larger, the interconnection scheme between FPGA chips becomes a bottleneck in prototype verification. [0003] An existing connection method between FP...

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Problems solved by technology

[0004] The embodiment of the present invention provides an ASIC chip verification method and a programmable gate array, aiming to solve the problems in the prior art that the connection method between FPGA chips occupies more I / O pin resources or needs to reduce the interface rate between modules to be verified question

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