Internal memory interface circuit framework supporting multi-internal memory standard and implementation thereof on metal oxide semiconductor (MOS) process

Abstract

The invention belongs to the field of complementary metal oxide semiconductor (CMOS) integrated circuits and discloses hybrid multimode internal memory interface support technology for a CMOS integrated circuit apparatus. The technology can support four or more internal memory standards by only modifying a double data rate 2 (DDR2) or DDR3 supporting interface circuit and adding certain auxiliary circuits without remarkably increasing an area or power consumption. The technology is suitable for designing a central processing unit (CPU), a system on chip (SoC), an application specific integrated circuit (ASIC) and other application chips adopting internal memory interfaces so as to improve flexibility and compatibility. An implementation method described by the invention is applied to a 65-nanometer tape-out process for two times and is verified. Infringement of the invention can be generally judged by analyzing an implementation circuit or by a backward analysis method for dissecting and photographing the chip of the circuit under the condition that the circuit cannot be obtained. Institutes which may infringe include various field-containing and field-free chip design companies, research institutes, schools and the like.

Description

1. Technical field [0001] The patent of the invention belongs to the field of CMOS integrated circuits. It is aimed at memory interface related chips of CMOS integrated circuits, covering all memory standards, including SDR SDRAM.Mobile SDRAM, DDR / DDR2SDRAM, mobile SDRAM, DDR3 SDRAM. This patent is not limited to a certain integrated Circuit production process, which covers 0.35um, 0.25um, 0.18um, 0.13um, 90nm, 65nm, 45nm, 32nm and shrink processes related to these processes. This technology is applicable to the design of CPU, SoC, ASIC and other application chips using memory interface to improve their flexibility and compatibility. 2. Technical background [0002] With the continuous improvement of semiconductor manufacturing technology and the continuous improvement of chip design capabilities, the functions of various processors are also improving rapidly, and higher requirements are put forward for the capacity and speed of memory. Memory technology is also constantly ...

AI Technical Summary

Problems solved by technology

To support multiple interface standards, the easiest way is to put several different interfaces together, but this will not only increase the area dramatically, but also increase power consumption and reduce performance due to the increase in input and output loads

The increase of the area will lead to a series of problems, including the increase of cost, the decrease of yield rate, and the integration of chips becomes more complicated or even impossible.

Not only that, because different memory interface standards also use different I / O voltages, so different power supply networks need to be used, which will increase the cost of the chip and lead to potential chip failure, so the design of the multi-mode interface cannot be a simple overlay

Images