Manufacturing method of memory with double-layer stacking self-alignment grid structure
A manufacturing method and self-alignment technology, which is applied in semiconductor/solid-state device manufacturing, electrical components, circuits, etc., can solve the problems of lower polysilicon and substrate loss of storage capacity, lower product performance, loss of storage content, etc., to reduce instantaneous The probability of high current breakdown tunneling oxide layer, improving product yield and reliability, and the effect of improving overall yield and reliability
Active Publication Date: 2012-04-18
SHANGHAI HUAHONG GRACE SEMICON MFG CORP
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[0012] 1. To a lesser extent, it is only a drop in withstand voltage capability, which can be erased and written under low voltage, resulting in partial storage errors
Or the electrons stored at high temperature can be released to the substrate through the tunnel oxide layer without an external voltage, resulting in the loss of stored content
[0013] 2. If the degree is serious, it will cause the lower polysilicon and the substrate to be directly short-circuited and lose the storage capacity, and become a storage bad area
[0014] The above situations will greatly reduce the performance of the product and lead to a decline in the yield
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[0034] The present invention will be described in further detail below in conjunction with the accompanying drawings and embodiments.
[0035] As shown in FIG. 3 , the present invention provides a method for improving the yield rate of a memory with a double-layer stacked self-aligned gate structure, and the process steps are as follows:
[0036] (1) Form the gate oxide layer 4 and the tunnel oxide layer 5 on the silicon substrate 8 (by growing a protective layer (usually SiO2, but very thick) on the silicon substrate 8, and then remove the gate by photolithography Oxygen layer, and then grow to form a gate oxide layer 4 and a tunnel oxide layer 5), on the gate oxide layer 4 and tunnel oxide layer 5, the lower polysilicon 3 and the intermediate insulating layer 2 are sequentially deposited; wherein the intermediate insulating layer 2 is Mixed layer of oxide, nitride or ONO structure (oxide, nitride and oxide), see Figure 3A .
[0037] (2) Photolithography (to protect two ga...
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The invention discloses a manufacturing method of a memory with a double-layer stacking self-alignment grid structure, comprising the following steps of: (1) forming a grid electrode oxidization layer and a tunneling oxidization layer on a silicon substrate, and sequentially depositing a lower polycrystalline silicon layer and a middle insulating layer on the grid electrode oxidization layer and the tunneling oxidization layer; (2) photoetching: etching the middle insulating layers until reaching to the lower polycrystalline silicon layer; (3) comprehensively depositing an upper polycrystalline silicon layer; (4) photoetching: etching the upper polycrystalline silicon layer till the stopping of the grid electrode oxidization layer to form a double-layer polycrystalline silicon grid structure with the upper polycrystalline silicon layer, the middle insulating layer and the lower polycrystalline silicon layer; and (5) carrying out subsequent process: removing residual grid electrode oxidization layer, and finally forming the memory with the double-layer stacking self-alignment grid structure. The method can reduce the product failure caused by PID (Proportion Integration Differentiation) and improves integral finished-product rate and reliability.
Description
technical field [0001] The invention belongs to a manufacturing process method of a semiconductor device, in particular to a manufacturing method of a double-layer stacked self-aligned gate memory with a tunnel oxide layer structure. Background technique [0002] In semiconductor devices, a double-layer stacked self-aligned gate memory with a tunnel oxide structure is a commonly used memory structure. Its basic structure is as follows: figure 1 Expressed. The transistor with the tunnel oxide layer can couple the electrons in the substrate channel through the tunnel oxide layer to the underlying polysilicon for storage or store the electrons stored in the underlying polysilicon through the tunneling oxide under the action of the vertical direction voltage. The layers are released to the substrate, which can correspond to the two states of storage respectively. When the voltage in the vertical direction is lower than the operating voltage, the tunnel oxide layer acts as an i...
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IPC IPC(8): H01L21/8239H01L21/283H01L21/311H10B99/00
Inventor王雷
OwnerSHANGHAI HUAHONG GRACE SEMICON MFG CORP