Built-in system test method of multiple static random access memory (SRAM) based on scanning test

Abstract

The invention discloses a built-in system test method of multiple static random access memory (SRAM) based on scanning test, belonging to the technical field of an integrated circuit design. Multiple SRAM to be tested are tested in the scanning mode and the built-in system test mode. In the scanning mode, all of the common triggers in the SRAM logic are replaced by the scanning triggers, and the scanning triggers are connected together to form a scanning chain. The test vector generated in the design stage is output by an automatic scanning test device, and the output of the chip is observed to judge whether the result is correct or not. In the built-in system test mode, through the starting of the built-in system test, the output signal is observed to judge whether the error is existing or not. In the method of the invention, too many logic circuits are not added the advantages of the scanning test and advantages of the built-in system test are combined, the system resource in maximum optimized, the test coverage is enhanced, the test time and test cost are saved, and the chip area saved.

Description

technical field [0001] The invention relates to a built-in self-test method of multiple SRAMs based on scan test, which belongs to the technical field of integrated circuit design. Background technique [0002] Recently, with the expansion of integrated circuit design scale and the improvement of system operating speed, integrated circuit testing has become an extremely important link in the process of integrated circuit design. With the development of system-on-chip design, among many embedded IP cores, SRAM core occupies an important position, so the test of embedded SRAM has become particularly important. The common fault types of SRAM in integrated circuits include: stuck-at fault, open circuit fault, jump fault, coupling fault, and address decoding fault. For these common faults, built-in self-test (Built In-System Test, BIST) is currently the mainstream testing method in the field of integrated circuit SRAM testing. The memory is composed of storage units with the sa...

AI Technical Summary

Problems solved by technology

This paper describes a typical SRAM built-in self-test method, but due to algorithm limitations and structural limitations, the test coverage is relatively low, and the test method is not suitable for the design of multiple SRAMs

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