Measuring structure for improving accuracy of exposure conditions

Abstract

The invention provides a measuring structure for improving the accuracy of exposure conditions, belonging to the technical field of semiconductors. The measuring structure comprises a main graph and a dummy graph, wherein the dummy graph is located beside the main graph; the density of the whole graph of the measuring structure is similar to the density of the graph in a device area inside the chip so that the measuring graph and the graph of the device area inside the chip are ensured to have approximately identical grinding velocity in the chemical and mechanical polishing process and the whole wafer is ensured to be more flattened. During photoetching exposure, the measuring graph and the optimum imaging focus in the device area inside the chip are located on the same plane, and the exposure condition defined by measuring the measuring graph is the optimum exposure condition of the graph of the device area inside the chip, thereby the accuracy of the photoetching exposure condition is effectively improved without affecting the capacity.

Description

technical field [0001] The invention relates to semiconductor photolithography exposure technology, in particular to a measurement structure for determining exposure conditions, and belongs to the field of semiconductor technology. Background technique [0002] In the manufacturing process of semiconductor chips and devices, a measurement structure including measurement patterns is usually arranged in the dicing line on the surface of the wafer to determine the photolithographic exposure conditions of the entire wafer. In the prior art, when performing photolithography, the optimum exposure conditions of the entire wafer can be defined and the process window can be judged by measuring only the measurement pattern located in the dicing line. In the prior art, the method of defining the exposure conditions of the entire wafer by only measuring the measurement pattern located in the dicing line has very high requirements for the flatness of the wafer surface. Only when the wafe...

AI Technical Summary

Problems solved by technology

However, increasing the measurement points will inevitably increase the area for testing on the wafer surface. For highly integrated chips and related devices, the production capacity will be greatly reduced. For the production of chips and devices, especially highly integrated The production of high-speed chips and devices has a greater impact

Images