Allowance gain circuit for analog-to-digital converter in pipeline structure

Abstract

The invention belongs to the technical field of integrated circuits, in particular to an allowance gain circuit for an analog-to-digital converter in a pipeline structure. The allowance gain circuit at least comprises an operational amplifier, four comparators, three sampling capacitors, a feedback capacitor, six switches, an adder and a coding circuit, wherein results of the comparators are added through the adder and used for controlling the switches through the coding circuit. In the invention, the calibration range of the offset voltage of the comparators is increased by increasing the number of partial comparators and rearranging the positions of the comparators, and an obvious effect can be achieved especially in the allowance gain circuit of a multi-bit structure at each level.

Description

technical field [0001] The invention belongs to the technical field of integrated circuits, and in particular relates to a margin gain circuit for an analog-to-digital converter with a pipeline structure. Background technique [0002] Due to its excellent performance in conversion rate, conversion accuracy and power consumption, the pipeline structure analog-to-digital converter is widely used in digital base stations, radar and other fields. Compared with other analog-to-digital converters, a special feature of the pipeline-structured analog-to-digital converter is that it allows the comparator to have a certain degree of offset without affecting the correctness of the final output result. In the most traditional 1.5bit / stage residual gain circuit structure (such as figure 1 shown), the comparator 1, 2 offset voltage is at are allowed within, such as figure 2 shown. This feature greatly reduces the design difficulty of the comparator, and also provides considerable to...

AI Technical Summary

Problems solved by technology

The allowable comparator offset of the 2.5bit / stage headroom gain circuit is 125mV, while the allowable comparator offset of the 3.5bit / stage headroom gain circuit is reduced to 62.5mV, which poses a high challenge to designers. requirements, and in some demanding designs even unattainable

However, once the offset voltage of the comparator is not well controlled and exceeds the correctable range, the output code of the analog-to-digital converter will be wrong, which will seriously affect the function realization of the analog-to-digital converter

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