Multi-chip parallel test method for clock asynchronous chips on wafer

Abstract

The invention discloses a multi-chip parallel test method for clock asynchronous chips on a wafer, which comprises the following steps: 1, based on process control, using an algorithmic pattern generator or an ordered vector generator of automatic test equipment to generate synchronous signals, and loading the synchronous signals onto all chips to be tested; 2, under the control of capture enabling, guiding an output end to a digital capturing module based on the function of a matrix, wherein the digital capturing module is provided with a high-frequency sampling clock; and sampling the signals in accordance with sampling clock frequency = N*excited clock frequency, wherein N is a positive integer which is greater than or equal to 3; 3, storing the sampled data in an address fail memory, wherein a response signal of one chip to be tested occupies one row in the address fail memory, and by parity of reasoning, the N objects to be tested occupy N-row space of the address fail memory; and 4, analyzing each row of data in the address fail memory. The invention can effectively shorten the test time.

Description

technical field [0001] The invention relates to a semiconductor chip testing method, in particular to a clock asynchronous chip testing method. Background technique [0002] Generally, in the DFT (Design ForTestability) design of the clock asynchronous chip, the response of the clock asynchronous chip is designed as a level signal, but in some special cases, this function cannot be realized, or It cannot be realized, and can only be solved by testing the algorithm. [0003] When testing multiple chips on the wafer, the test equipment can only generate the same excitation signal and the same comparison signal and send them to all the chips under test. For the clock asynchronous chip, after receiving the same excitation signal at the same time, the response time of each chip under test will be different, and the comparison signal sent by the test equipment can only be sent at the same time, so it will not be possible to realize simultaneous testing of multiple chips. The pas...

AI Technical Summary

Problems solved by technology

For the clock asynchronous chip, after receiving the same excitation signal at the same time, the response time of each chip under test will be different, and the comparison signal sent by the test equipment can only be sent at the same time, so it will not be possible to realize simultaneous testing of multiple chips. Chip pass / failure judgment

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