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Synchronous first input first output (FIFO) circuit system

A circuit system and unit circuit technology, applied in the direction of electrical digital data processing, data conversion, instruments, etc., can solve difficult problems such as area optimization

Active Publication Date: 2012-10-31
SHANGHAI HUAHONG INTEGRATED CIRCUIT
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

As the storage depth deepens, the scale of the read and write pointer control circuits also increases accordingly, and the chip area increases accordingly, and it has to rely on automatic layout and wiring tools to realize the layout, so it is difficult to achieve area optimization

Method used

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  • Synchronous first input first output (FIFO) circuit system
  • Synchronous first input first output (FIFO) circuit system

Examples

Experimental program
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Embodiment Construction

[0015] In some designs such as the memory management module, the data involved in the write operation is non-zero data, and the read and write operations of the data occur in different clock cycles, so the traditional synchronous FIFO circuit system usually has two independent read , Write pointer control circuit can be improved completely.

[0016] see figure 1 As shown, the basic storage unit circuit in an embodiment includes: a data selector module 110 ; a storage unit module 120 ; a blocking logic module 130 ; and a read-write control logic module 140 .

[0017] The data selector module 110 , according to the control signal provided by the read / write control logic module 140 , selects the data source to be latched in the next clock cycle from the data source 1 and the data source 2 as the input of the storage unit module 120 . Data source 1 is the data latched in the subsequent storage unit. Data source 2 is the data that needs to be stored for the write operation.

[0...

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PUM

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Abstract

The invention discloses a synchronous first input first output (FIFO) circuit system, comprising a plurality of basic storage cell circuits, wherein the basic storage cell circuits are connected in sequence in a cascading mode; congestion control output of the former basic storage cell circuit is taken as congestion control input of the latter basic storage cell circuit; the former congestion control input of a first basic storage cell circuit is 0, namely, the former congestion control input of the first basic storage cell circuit is non-congestion; the congestion control output of the last basic storage cell circuit is hung; the data output of the latter basic storage cell circuit is taken as input for the data source 1 of the former basic storage cell circuit; and the input for the data source 1 of the last basic storage cell circuit is 0. The system can fast customize domain, optimize area of an integrated circuit chip, and is applied to logic designs such as a memory management module and the like.

Description

technical field [0001] The invention relates to the field of digital circuit logic design, in particular to a cascade blocking synchronous FIFO (first in first out) circuit system with customizable layout. Background technique [0002] Synchronous FIFO is a commonly used functional module in digital circuit systems, mainly used to solve the storage problem of first-in-first-out data in logic design, and can perform synchronous read or write operations of data. The traditional synchronous FIFO is composed of three parts: read and write pointer control circuit and memory bank. As the storage depth deepens, the scale of the read and write pointer control circuits also increases accordingly, and the chip area increases accordingly, and it has to rely on automatic layout and wiring tools to realize the layout, so it is difficult to achieve area optimization. Contents of the invention [0003] The technical problem to be solved by the present invention is to provide a synchrono...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F5/10
Inventor 顾福敏季欣华
Owner SHANGHAI HUAHONG INTEGRATED CIRCUIT
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