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Method of forming an integrated circuit structure

An integrated circuit and seed layer technology, applied in the direction of circuits, electrical components, electrical solid devices, etc., can solve problems such as poor adhesion, bump peeling, increased manufacturing costs, etc., and achieve the effect of improving process robustness

Inactive Publication Date: 2014-06-18
TAIWAN SEMICON MFG CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

During subsequent processes, the bumps may delaminate due to poor adhesion between the copper seed layer and the electroplated copper
The above challenges result in lower bump yields and higher manufacturing costs, as well as poorer bump reliability

Method used

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  • Method of forming an integrated circuit structure
  • Method of forming an integrated circuit structure
  • Method of forming an integrated circuit structure

Examples

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Embodiment Construction

[0014] The making and using of various embodiments are described in detail below, however, it should be appreciated that these embodiments provide many applicable inventive concepts that can be implemented in a variety of specific contexts and that the specific embodiments discussed herein are only The descriptions are intended to illustrate specific ways to make and use the embodiments, not to limit the scope of the disclosure.

[0015] According to an embodiment, a new process for forming an integrated circuit is provided, and the intermediate stages of manufacturing an embodiment are illustrated. Next, various variations of the embodiments are discussed. Throughout the illustrated embodiments and various diagrams, like reference numerals are used to designate like elements.

[0016] refer to figure 1 , first providing a wafer 2 comprising a substrate 10 . The substrate 10 may be a semiconductor substrate, such as a bulk silicon substrate, which may contain other semicon...

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Abstract

A method of forming an integrated circuit structure includes forming a copper-containing seed layer on a wafer, and performing a descum step on an exposed surface of the copper-containing seed layer. The descum step is performed using a process gas including fluorine and oxygen. A reduction / purge step is then performed on the exposed surface of the copper-containing seed layer using a nitrogen-containing gas. A copper-containing layer is plated on the copper-containing seed layer.

Description

technical field [0001] The invention relates to a method for forming an integrated circuit structure, in particular to a process for forming bumps. Background technique [0002] When forming a semiconductor chip, integrated circuit elements, such as transistors, are first formed on the surface of the semiconductor substrate of the chip, and then interconnection structures are formed on the integrated circuit elements. Next, bumps are formed on the surface of the chip to facilitate the use of integrated circuit elements. [0003] In a typical bump forming process, an under-bump metallurgy (UBM) is formed first, and then a bump is formed on the under-bump metallurgy. Forming the UBM layer may include forming a copper seed layer, forming a mask on the copper seed layer and patterning the mask such that a portion of the copper seed layer is exposed through openings in the mask. Then, an electroplating step is performed to electroplate a thick copper layer on the exposed portio...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/60H01L23/00H01L21/02
CPCH01L2224/13111H01L2224/13139H01L2224/13083H01L2924/04941H01L2224/05124H01L2924/04953H01L2224/05139H01L2224/05027H01L2224/05568H01L2224/11849H01L2924/00013H01L2924/01047H01L2224/1147H01L2224/0381H01L2224/0347H01L21/0206H01L2924/01006H01L2924/01078H01L2224/13116H01L24/05H01L2224/94H01L2924/01073H01L24/11H01L2924/01079H01L2924/01074H01L2924/14H01L2224/13155H01L2224/05144H01L24/13H01L2924/01082H01L2224/0346H01L2224/13147H01L2924/01013H01L2224/05147H01L21/02068H01L2924/01022H01L24/03H01L2924/014H01L2924/01023H01L2224/0401H01L2224/05655H01L2224/1146H01L2924/01029H01L2924/01018H01L2224/13113H01L2224/05573H01L2924/01033H01L2224/81022H01L2924/01075H01L2924/0002H01L2224/0361H01L2924/00014H01L2224/11H01L2224/13099H01L2224/13599H01L2224/05599H01L2224/05099H01L2224/29099H01L2224/29599H01L2224/05552
Inventor 刘重希林正忠何明哲林国诚周孟纬
Owner TAIWAN SEMICON MFG CO LTD
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