Switch-body PMOS switch with switch-body dummies

Abstract

A sample-and-hold feed switch has parallel PMOS branches and parallel NMOS branches, each extending from an input node to an output node connected to a hold capacitor. Each PMOS branch has a PMOS switch FET connected to a matching PMOS dummy FET, and each NMOS branch has an NMOS switch FET connected to a matching NMOS dummy FET. A sample clock switches the PMOS switch FETs on and off, and a synchronous inverse sample clock effects complementary on-off switching of the PMOS dummy FETs. Concurrently, a synchronous inverse sample clock switches the NMOS switch FETs on and off, and the sample clock effects a complementary on-off switching of the NMOS dummy FETs. A bias sequencer circuit biases the bodies of the PMOS switch FETs and the bodies of the PMOS dummy FETs, in a complementary manner, and biases the NMOS switch FETs and the NMOS dummy FETs, also in a complementary manner. The on-off switching of the PMOS dummy FETs injects charge, cancelling a charge injection by the PMOS signal switch FETs, and injects glitches cancelling glitches injected by the PMOS signal switch FETs. The on-off switching of the NMOS dummy FETs injects charge that cancels a charge injection by the NMOS signal switch FETs, and injects glitches that cancels glitches injected by the NMOS signal switch FETs.

Description

technical field [0001] The present invention generally relates to circuits for sampling and holding instantaneous values ​​of time-varying electrical signals. Background technique [0002] A sample and hold circuit receives an electrical signal having one or more time-varying properties (eg, magnitude or phase) and acquires and holds samples of the signal in response to a sample command event (eg, a clock edge). [0003] Sample and hold devices (hereinafter generally referred to as "S / H devices") are used in many applications, for example, presamplers within or before the front end of an analog-to-digital converter ("ADC"), typically for Supplying a value to the ADC's comparator that is moderately stable for a long enough time to meet the ADC's setup and hold time requirements; or a "de-aliaser" ( de-glitter), typically used to sample the DAC output at some point after the DAC clock, and thus maintain a steady-state analog signal level. [0004] Ideally, the samples held b...

AI Technical Summary

Problems solved by technology

An inherent problem with single-transistor PMOS FET or NMOS FET structures is that they require a threshold gate-source voltage (commonly referred to as V TH ) to turn on, meaning that a conductive channel is formed extending from source to drain under the gate

Although these and other methods have been known for a long time, acceptable S / H device performance has not been achieved in many applications

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