Pipeline ADC employing integral non-linear error correction

Abstract

Provided is a circuit which comprises a pipeline analog/digital converter which converts an analog input signal to a digital output signal and a feedback circuit coupled with the converter, therefore, the digital output signal is adapted to have an average non linearity error value of about zero volt.

Description

field of invention [0001] The present invention relates to a method and system for reducing integral nonlinearity errors in a pipelined analog-to-digital converter (ADC). Background technique [0002] Analog-to-digital converters are widely used in various applications in the field of electronics industry, such as digital television processing and conversion of analog video to DVD video. One of the commonly used ADC types is the pipeline ADC. This ADC requires fewer components than a fast ADC (flashADC) that performs the same digital conversion. Typically, pipeline ADCs also perform conversions faster than SAR converters, where the conversion time is proportional to the number of bits to be converted. Therefore, pipelined ADCs are often suitable for applications that require relatively fast conversion times while keeping the number of circuit components to a minimum. [0003] A major drawback of pipelined ADCs is that they are prone to architecture-dependent integral nonl...

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Problems solved by technology

As a result, the error moves so quickly that it cannot be perceived by the human eye

But this technique only handl

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