Wet process method for improving chamfer smoothness on top of shallow trench isolation

A shallow trench and smoothness technology, applied in the field of wet process for improving the smoothness of the top chamfer of shallow trench isolation, can solve problems such as reducing the reliability of the device, improve the smoothness, increase the smoothness, and avoid the use of the device. The effect of reliability being affected

Active Publication Date: 2011-07-06
SHANGHAI HUAHONG GRACE SEMICON MFG CORP
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Problems solved by technology

The sharp chamfer affects the thickness of the gate oxide subsequently grown on it, which easily leads to the double hump (double peak) phenomenon of the Id-Vg (drain current-gate voltage) curve, reducing the reliability of the device

Method used

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  • Wet process method for improving chamfer smoothness on top of shallow trench isolation
  • Wet process method for improving chamfer smoothness on top of shallow trench isolation
  • Wet process method for improving chamfer smoothness on top of shallow trench isolation

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Embodiment Construction

[0015] The present invention will be described in further detail below in conjunction with the accompanying drawings and embodiments.

[0016] The method of the invention is mainly suitable for improving the smoothness of top chamfering in STI (Shallow Trench Isolation) modules. In order to improve this structure, a short-term wet APM (ammonia hydrogen peroxide mixture) liquid treatment is added after the nitride film is etched back, and the chamfer shape is adjusted by micro-etching silicon, while avoiding oxidation of the substrate. Overetching of the film. Since the chamfer is etched from the top and the side, it can increase the roundness of the top chamfer of the STI, and avoid affecting the reliability of the device.

[0017] The specific implementation process steps of the inventive method are as follows:

[0018] (1) shallow trench etching and removal of photoresist; as Figure 4A As shown, shallow trench etching can use photoresist 1 as a mask to complete nitride f...

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Abstract

The invention discloses a wet process method for improving chamfer smoothness on top of shallow trench isolation. The method comprises the following steps: (1) etching a shallow trench and removing photoresist; (2) etching a nitride film back, and cleaning with hydrofluoric acid; (3) adjusting the appearance of the chamfer on the top of the shallow trench isolation by wet APM liquor treatment; and (4) growing a substrate oxide film in the shallow trench. In the method, the wet APM liquor treatment is added after the back etching of the nitride film, the appearance of the chamfer is adjusted through micro-etching on silicon, and over etching to the substrate oxide film is avoided. The chamfer is etched in the upper side and the lateral side, so that the smoothness of the chamfer on the topof the shallow trench isolation (STI) can be increased, and the use reliability of the device is prevented from being influenced.

Description

technical field [0001] The invention relates to a semiconductor integrated circuit manufacturing process method, in particular to a wet process method for improving the roundness of top chamfering of STI (Shallow Trench Isolation). Background technique [0002] Shallow trench isolation (STI) is widely used in advanced logic circuit technology. The advantages and disadvantages of shallow trench isolation will directly affect the characteristics of the device. In the current process, during the formation of the STI module, in order to optimize the filling lateral morphology of the HDP (high-density plasma) oxide film and avoid filling voids, as well as to solve the subsequent defect problem, the nitride film is etched back and Subsequent hydrofluoric acid cleaning process. The top chamfer of the STI is sharpened by wet etching (see figure 1 ), and at the same time lead to sharper chamfers after the growth of the substrate oxide film and HDP filling (see figure 2 ). The s...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/762
Inventor 杨华陈昊瑜黄奕仙姚嫦娲
Owner SHANGHAI HUAHONG GRACE SEMICON MFG CORP
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