Method for reducing errors incapable of being corrected, memory device and controller thereof
A memory device and controller technology, applied in the field of error correction, can solve problems such as side effects, instability of multi-level cell flash memory, inability to take into account operational performance, system resource usage control, etc., to achieve the goal of saving consumption, taking into account operational performance, and optimal performance Effect
Active Publication Date: 2011-08-03
SILICON MOTION INC (CN)
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Problems solved by technology
However, problems caused by the instability of multi-level cell flash memory have also emerged one by one
In view of these many problems, although related technologies provide some solutions, they are always unable to take into account the operational efficiency and system resource usage control
Therefore, no matter which solution is adopted, there will often be corresponding side effects
Method used
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[0055] Please refer to figure 1 , figure 1 It is a schematic diagram of a memory device 100 according to a first embodiment of the present invention, wherein the memory device 100 can represent a portable memory device (for example: a memory card conforming to SD / MMC, CF, MS, XD standards) or a solid-state hard disk ( Solid State Drive, SSD) and other memory devices. The memory device 100 includes: a flash memory (Flash Memory) 120 ; and a controller for accessing (Access) the flash memory 120 , wherein the controller is, for example, a memory controller 110 . According to this embodiment, the memory controller 110 includes a microprocessor 112, a read only memory (Read Only Memory, ROM) 112M, a control logic 114, a buffer memory 116, and an interface logic 118, wherein the control logic 114 includes Multiplexers 1142 and 1146 , an Error Correction Code (ECC) decoder 1144 , and a majority decision module 1148 . Here, the buffers B( 1 ) and B( 2 ) may represent different buf...
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The invention relates to a method for reducing errors incapable of being corrected with respect to error correction codes in a memory device. The method comprises the following steps of: carrying out a majority rule based on data of the same address read at different times to generate majority rule data corresponding to the address; and checking whether the majority rule data has errors incapableof being corrected to decide whether the majority rule data is output to be used as the data of the address. The invention further relates to a relevant memory device and a controller thereof. The invention can be used for reducing errors incapable of being corrected with respect to error correction codes in the memory device. In addition, the invention can give consideration to operational efficiency and system resource use control and management without relevant technical problems, such as wrongly marking some blocks as bad blocks. Furthermore, the capacity of a buffer region / buffer device can be saved and the data at the last time and the majority rule data are ready for use during the reading of the data at the last time, so that the best efficiency is provided.
Description
technical field [0001] The present invention relates to the technical field of error correction of flash memory (Flash Memory) control chips, more specifically, to a method for reducing uncorrectable errors related to Error Correction Code (ECC) in a memory device and related Memory device and its controller. Background technique [0002] In recent years, due to the continuous development of flash memory technology, various portable memory devices (for example: memory cards conforming to SD / MMC, CF, MS, XD standards) or solid state hard drives (Solid State Drive, SSD) with flash memory are widely used. implemented in many applications. Therefore, the access control of the flash memory in these memory devices has become a very hot topic. [0003] As far as the commonly used NAND flash memory is concerned, it can be mainly divided into two types of flash memory: single level cell (Single Level Cell, SLC) and multiple level cell (Multiple Level Cell, MLC). Each transistor in...
Claims
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IPC IPC(8): G06F11/10
Inventor 杨宗杰
Owner SILICON MOTION INC (CN)