Flash memory devices having multi-bit memory cells therein with improved read reliability

Abstract

Integrated circuit memory devices include an array of nonvolatile N-bit memory cells, where N is an integer greater than one. Control circuitry is also provided to reliably read data from the N-bit memory cells. This control circuitry, which is electrically coupled to the array, is configured to determine, among other things, a value of at least one bit of data stored in a selected N-bit memory cell in the array. This is done by decoding at least one hard data value and a plurality of soft data values (e.g., 6 data values) read from the selected N-bit memory cell using a corresponding plurality of unequal read voltages applied to the selected N-bit memory cell during a read operation.

Description

[0001] Priority Application Citation [0002] This application claims priority to Korean Patent No. 10-2010-0011554 filed on Feb. 8, 2010, the contents of which are incorporated herein by reference. technical field [0003] The present invention relates to semiconductor memory devices, and more particularly, to flash memory devices and methods of operating the same. Background technique [0004] Semiconductor memory devices are generally classified into volatile memory devices (eg, DRAM and SRAM) and nonvolatile memory devices (eg, EEPROM, FRAM, PRAM, MRAM, and flash memory). A volatile memory device loses data stored therein when its power supply is interrupted, while a nonvolatile memory device retains data stored therein even when its power supply is interrupted. In particular, flash memory devices are widely used as storage media in computer systems due to their fast programming speed, low power consumption, and large storage capacity. [0005] In a flash memory device...

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Problems solved by technology

[0007] However, the voltage window available for the threshold voltage distribution is limited

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