Cache memory, memory system and control method therefor

Abstract

Disclosed is an L2 cache (202) provided with a first port (211) for inputting commands from a CPU (201); a third port (213) for inputting commands from a DMAC (205); a bit decision unit (71) in which it is determined whether or not the data of an address specified in the command is stored in the L2 cache (202) when a command is input to the third port (213); and a DMAC access controller (63) in which processing is conducted to maintain the coherency of the data stored in a memory (204) and the stored data when a command is input to the third port (213) and the decision by the bit decision unit (71) is that the command is stored, and the input command is output to a memory (204) as the command output from the DMAC (205).

Description

technical field [0001] The present invention relates to a cache memory, a memory system, and a control method thereof, in particular, a cache memory that stores a part of data stored in a main memory in response to an access from a processor, and a memory system including the cache memory. Background technique [0002] In recent memory systems, for example, a small-capacity and high-speed cache memory composed of SRAM (Static Random Access Memory, Static Random Access Memory) or the like is disposed inside or near a microprocessor. In such a memory system, the memory access of the microprocessor is made high-speed by storing part of the data read by the microprocessor from the main memory and part of the data written into the main memory in a cache memory (cache). change. [0003] Figure 14 is a diagram showing the configuration of a conventional memory system 100 . Figure 14 The shown memory system 100 has a CPU 101 , a cache memory 102 , a memory controller 103 , a memo...

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Problems solved by technology

[0022] but, Figure 15 The shown memory system 110 is required to have the bus 106, so, with Figure 14 Compared with the memory system 100 shown, there is a problem of increased area

This problem is particularly prominent when the memory system 110 contains multiple master devices such as DMAC105

[0023] In addition, when a plurality of bus protocols are used as the protocol used for data transfer between the DMAC 105 and the memory 104, there is a problem that the interface between the DMAC 105 and the cache memory 102 becomes complicated.

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