Hardware coprocessing device for high-speed mass data acquisition and storage system

A technology of massive data and storage system, applied in the direction of digital variable display, etc., can solve the problem that it cannot be well applied to high-speed massive data acquisition system.

Active Publication Date: 2011-09-28
UNI TREND TECH (CHINA) CO LTD
View PDF6 Cites 8 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0013] In the high-speed mass data acquisition system, the sampling rate of the system will be further improved, and the speed of the...

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • Hardware coprocessing device for high-speed mass data acquisition and storage system
  • Hardware coprocessing device for high-speed mass data acquisition and storage system
  • Hardware coprocessing device for high-speed mass data acquisition and storage system

Examples

Experimental program
Comparison scheme
Effect test

Embodiment

[0042] Such as figure 1 As shown, after the analog signal is conditioned by the channel conditioning circuit 1, the output differential signal is simultaneously sent to the analog-to-digital converter 2 for alternate sampling with a 1.5GHz clock with a phase difference of 90 degrees, and four 1.5GHz data streams are obtained and processed. Serial-to-parallel conversion, output 8 750MHz data streams and 375MHz AD differential clock input FPGA (field programmable logic gate array) for phase-splitting storage.

[0043] In this embodiment, the hardware co-processing devices of the high-speed mass data acquisition system are all designed in FPGA except for the large-capacity dynamic memory. Such as figure 1 As shown, the hardware co-processing device of the high-speed mass data acquisition and storage system of the present invention includes an input serial-to-parallel conversion logic unit 301, a time base circuit 302, a hardware co-processing multi-level screening unit 303, a ha...

example

[0108] If the hardware co-processing technology is not used, the system needs T1≈10759.7s to observe the 512Mpts waveform. However, after using hardware co-processing and hardware post-processing technology, the efficiency is significantly improved. Under the condition of storage depth of 512Mpts: set the waveform address quick lock and mapping technology screening ratio to N; there are 10 user-concerned sample data on the screen; the sampling rate is R D ; System efficiency ratio comparison table, as shown in Table 1:

[0109] Table 1 Storage efficiency comparison table

[0110]

[0111]

[0112] Table 1

[0113] The results show that the efficiency and waveform capture rate of the system can be greatly improved by adopting technologies such as multi-level screening and address quick lock under hardware co-processing, hardware post-processing and FIFO real-time control.

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to view more

PUM

No PUM Login to view more

Abstract

The invention discloses a hardware coprocessing device for a high-speed mass data acquisition system. During detailed waveform observation, one path of data flow (1) shunted from high-speed mass data flow with increased bit width and reduced speed by a time-base circuit enters a hardware coprocessing multi-stage screening unit; N continuous numerical values of the data flow (1) are screened; the screened coprocessing data is sent into hardware coprocessing FIFO (First In First Out) to be stored; the other path of the flow data (1) flows to the data FIFO of a DDR2 (Double Data Rate 2) controller and is stored in a DDR2 high-capacity dynamic memory under the control of the DDR2 controller; a user performs profile observation according to the coprocessing data in the hardware coprocessing FIFO; and the start address and the destination address of waveform needing detailed observation are sent to an addressing counter, and addressing is performed on the high-capacity dynamic memory, and the observation waveform data the user concerns is read quickly and sent to a display screen for displaying. According to the invention, through the increasing of the bit width of a high-speed mass data flow, the speed of the high-speed mass data flow can be reduced.

Description

technical field [0001] The invention belongs to the technical field of data collection and storage systems, and more specifically relates to a hardware co-processing device of a high-speed mass data collection and storage system. Background technique [0002] With the development of A / D converters (ADC) and the maturity of time-alternative parallel sampling technology, the sampling rate of digital systems is getting higher and higher. The processing capability puts forward new requirements; at the same time, with the increase of storage depth, the processing time of digital waveform recording is lengthened, which greatly reduces the waveform capture rate of the system. It can be seen that improving the storage depth while solving the problems of slow response speed and low waveform capture rate is one of the key technical problems faced by the development of data acquisition and storage systems. [0003] The three main performance indicators of the data acquisition and stor...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to view more

Application Information

Patent Timeline
no application Login to view more
IPC IPC(8): G01R13/02
Inventor 曾浩叶芃宋鹏飞黄武煌邱渡裕向川云
Owner UNI TREND TECH (CHINA) CO LTD
Who we serve
  • R&D Engineer
  • R&D Manager
  • IP Professional
Why Eureka
  • Industry Leading Data Capabilities
  • Powerful AI technology
  • Patent DNA Extraction
Social media
Try Eureka
PatSnap group products

Browse by: Latest US Patents, China's latest patents, Technical Efficacy Thesaurus, Application Domain, Technology Topic.

© 2024 PatSnap. All rights reserved.Legal|Privacy policy|Modern Slavery Act Transparency Statement|Sitemap