Low-heat-resistance packaging structure of power MOS (Metal Oxide Semiconductor) device

Abstract

The invention discloses a low-heat-resistance packaging structure of a power MOS (Metal Oxide Semiconductor) device, belonging to the technical field of power semiconductor devices. In the invention, the silicon chip flip bridge clip technology and the conventional TO packaging technology are combined, and a flip heat-radiation structure is used so that the heat generated by the power MOS device directly flows to a metal heat sink, the problem of overhigh heat resistance caused by the conventional TO packaging of the power MOS device is solved; the large area contact of the bridge clip technology achieves the reduction of the heat resistance, the increment of the current capacity and the decrement of the parasitic inductance. The low heat resistance packaging structure of the power MOS device, provided by the invention, has the appearance of the conventional TO packaging; the power MOS device with excellent performance is packaged without adding the packaging equipment, but only properly increasing the related equipment of the bridge clip and the flip technique. The low heat resistance packaging structure of the power MOS device, provided by the invention, has about 80% of reducedheat resistance, about two times of increased current capacity and largely reduced parasitic inductance compared with the conventional TO packaging structure through the proving of the actual testing.

Description

technical field [0001] The invention belongs to the technical field of power semiconductor devices and relates to a package structure of power MOS devices. Background technique [0002] The packaging of power semiconductor devices usually refers to the installation of a housing for semiconductor devices on a silicon chip. It not only protects the chip and enhances thermal conductivity, but also serves as a bridge between the internal world of the chip and the external circuit and a common function of specifications. The main function of packaging is to provide physical protection and electrical connection for the chip, and at the same time realize the standardization and normalization of the shape of semiconductor devices or integrated circuits. [0003] Because the chip must be isolated from the outside world, to prevent the impurities in the air from corroding the chip circuit and causing electrical performance degradation, protect the chip surface and connecting leads, et...

AI Technical Summary

Problems solved by technology

[0007] Although the bridge clip technology similar to DirectFET can greatly reduce the thermal resistance and parasitic inductance of MOS devices, and the increase of the contact surface also greatly increases the current capacity, but its leadless packaging technology is not compatible with existing pins. There are great differences in packaging forms, which are not compatible with existing technologies and require a large investment in packaging equipment

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