Thermal-expandability three-dimensional parallel cooling integration method, namely, on-chip system key technology for massively parallel computation

Abstract

The invention belongs to the field of integrated circuit design, and in particular relates to a thermal-expandability three-dimensional parallel cooling integration method. The three-dimensional vertical integration technology proposed at present has disability in thermal expansion. The invention provides a thermal-expandability three-dimensional parallel cooling integration method. In the figure 1 described in the specification, all device layers are parallel with a cooling direction, each device layer is in a shape of a strip, short sides of the strip are parallel to the cooling device, and long sides of the strip are vertical to the cooling device, therefore each device layer is ensured to obtain an independent and shorter cooling channel by virtue of a high-thermal-conductivity silicon substrate (instead of thermal-conducting through holes) installed on the device layer and the fact that the highest temperature of a thermal-expandability three-dimensional parallel cooling integrated chip has no relation with the number of overlapped device layers is ensured. The invention also provides an analysis model for calculating the highest substrate temperature of the thermal-expandability three-dimensional parallel cooling integrated chip, and an analytic expression of the highest substrate temperature of a three-dimensional chip is derived, therefore the thermal expandability of the method disclosed by the invention can be proved theoretically. The method can be widely applied to a three-dimensional integration scheme-based massively parallel computation on-chip system needing good cooling performance urgently.

Description

Technical field: [0001] The invention belongs to the field of integrated circuit design, and in particular relates to a thermally expandable three-dimensional parallel heat dissipation integration method. Background technique: [0002] 3D chip technology has been extensively studied as a candidate technology capable of continuing Moore's Law (refer to Comparative Documents 1-10). In order to improve performance and reduce design complexity, on-chip integrated parallel computing technology is widely used in the field of high-end computing, and multi-core system-on-chip (MPSoC) has become an important research direction of integrated circuit design (refer to reference documents 2, 10). In order to maximize performance, thousands of computing units must be integrated in the chip in the future (refer to reference document 10), which requires a higher level of integration, and only 3D integration technology can provide such a high level of integration. [0003] At present, 3D ve...

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Problems solved by technology

[0016] Aiming at the defect that the existing three-dimensional vertical integration technology cannot achieve thermal expansion, is limited by too high temperature, and cannot maximize performance through the stacking of many device layers, the present invention proposes a thermally expandable 3D Parallel heat dissipation integration method, that is, each device layer is parallel to the heat dissipation direction, and the device layer is elongated, its short side is parallel to the heat dissipation direction, and its long side is perpendicular to the heat dissipation direction, thus ensuring that each device layer can rely on its own The high thermal conductivity silicon substrate (rather than thermal vias) is used to obtain independent and short heat dissipation channels, ensuring that the maximum temperature of the 3D parallel heat dissipation integrated chip has nothing to do with the number of stacked device layers

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