39 results about "Massively parallel computation" patented technology

The invention discloses a multi-dimensional operation data analysis and method based on a BI system, and relates to the technical field of multi-dimensional operation data analysis, and the system comprises a data integration module which is in butt joint with real-time data of a business system through a BI platform; the data logic processing module adopts a streaming computing framework to compute and update data in real time, and the timed task layer configures periodic batch tasks and executes historical data aggregation, trend analysis and cross-module association computation; the data warehouse module is used for storing the processed data and carrying out classified storage according to business dimensions to form a unified business data warehouse; the distributed computing engine module is used for scheduling and distributing tasks; and the visual report module is used for generating a multi-dimensional operation analysis report. Through real-time data integration, streaming computation and timed task configuration, efficient data processing and personalized requirements are supported, large-scale parallel computation and load balancing are supported, and disaster recovery capacity is enhanced.

According to the chip system, the data transmission method and the related equipment provided by the embodiment of the invention, the chip system comprises IO core particles and a plurality of calculation core particles, each calculation core particle is configured with a corresponding core particle center, and each calculation core particle is connected with at least two physical interconnection ports in the IO core particles through the core particle center; the core grain center comprises a splitting unit and a merging unit, and the splitting unit is used for distributing data streams sent by the computing core grains to at least one physical interconnection port according to service types; the merging unit is used for recombining the data stream received from the physical interconnection port or directionally forwarding the data stream to the computing core grain, and the data throughput rate and the overall transmission efficiency in a large-scale parallel computing scene are remarkably improved on the premise that the hardware specification of the external IO core grain does not need to be modified.

The invention discloses an artificial intelligence model dynamic reasoning method and system based on a consumer-level heterogeneous chip, and relates to the technical field of artificial intelligence and computer processing. The method is operated on a heterogeneous processor integrating a CPU (Central Processing Unit), a GPU (Graphics Processing Unit) and an NPU (Network Processing Unit), by monitoring hardware states such as load, temperature and available memory in real time and combining an AI model hierarchical structure and operator characteristics, reasoning calculation tasks are dynamically allocated to an optimal processing unit, namely, the CPU is responsible for task arrangement and serial logic, the GPU executes large-scale parallel calculation, and the NPU processes and optimizes a neural network layer. And the results are integrated cooperatively. The system adopts a dynamic inference engine, realizes efficient and low-energy-consumption operation of a large-scale AI model on resource-constrained equipment, improves response speed, protects local data privacy, and is suitable for various consumer electronics needing AI capability.

The invention provides an AI multi-agent and digital twinborn fusion production scheduling process visualization method, medium and system, and belongs to the technical field of AI multi-agent production scheduling. Large-scale parallel computing is achieved by constructing a GPU three-layer CUDA processing architecture, a first layer data preprocessing grid executes data cleaning in parallel, a second layer data preprocessing grid executes data cleaning in parallel, and a third layer data preprocessing grid executes data cleaning in parallel; the second layer of negotiation analysis grid operates an agent interaction recognition model based on Transform to perform parallel mode recognition, the third layer of visual calculation grid operates an LSTM-CNN fused production scheduling process mapping model to generate visual data, and calculation resource allocation is dynamically adjusted through a multi-head attention mechanism. The calculation performance is optimized by adopting a pipeline parallel and data parallel strategy, and the memory access delay is hidden by combining an asynchronous data transmission and calculation overlapping technology, so that the technical problem that the real-time parallel processing of the multi-agent high-frequency negotiation data cannot be realized is solved.

The invention provides a terahertz communication sensing and computing integrated system based on hierarchical resource scheduling and mixed waveforms. The system comprises a unified radio frequency front end which adopts a high-integration-level terahertz phased array chip and supports ultra-large bandwidth transmission and flexible multi-beam forming; the baseband processing unit (BBU) is used for realizing real-time processing and large-scale parallel computing of signals; the OCSE waveform generation module is used for generating an ''orthogonal traffic signal-perception embedded (OCSE)'' waveform; the parallel receiver processing module comprises a communication demodulation path and a sensing parameter extraction path which are arranged in parallel; and the three-layer intelligent resource scheduler constructs an application-function-physics three-layer closed-loop scheduling model based on a deep reinforcement learning (DRL) algorithm, and is used for dynamically adjusting the distribution proportion of physical resources between communication and sensing functions according to an upper-layer application real-time task demand and a bottom-layer physical environment sensing result so as to maximize the comprehensive efficiency of the system.

The invention provides a model correction method supporting large-scale parallel computing, which relates to the technical field of semiconductor manufacturing, and can accurately correct a model according to the distribution characteristics of input data and the variation trend of errors in an iteration process by dynamically adjusting physical constraints according to data distribution characteristics and error feedback in a correction process. The constraint condition of a physical model is optimized in real time, the precision and adaptability of the model are remarkably improved, a local optimal solution can be effectively avoided, and it is ensured that an output result better conforms to the physical law, so that higher prediction reliability is achieved in semiconductor manufacturing, meanwhile, the number of iterations caused by improper initial parameters is reduced, the calculation efficiency is optimized, and the reliability is improved. According to the method, collaborative optimization of global and local correction is achieved in parallel computing supporting tens of thousands of CPUs, the computing speed and the resource utilization rate are greatly increased, the robustness and expandability of the method are enhanced, the method can seamlessly process the data scale from the GB level to the TB level, and the method is suitable for industrial environments with different hardware configurations.

According to the large rotary equipment assembling unbalance optimization method based on GPU parallel acceleration and the video memory control technology, inherent attributes of a rotor are stored in a CUDA constant memory, a dynamic combination batch scheduling mechanism is adopted, and GPU computing resources can be fully utilized in a high-dimensional optimization space of million-level phase combination; and while the calculation accuracy is ensured, the use pressure of a video memory is remarkably reduced, kernel operation interruption and system crash are effectively avoided, and stable execution of a large-scale parallel calculation task is ensured.

The invention provides a millimeter-wave radar boiler heating surface tube crack detection method based on GPU parallelization, and the method comprises the steps: constructing a three-layer parallelization frame integrating data flow, calculation and control, and employing the large-scale parallel calculation capability of a GPU to detect the crack of a heating surface tube of a millimeter-wave radar boiler. The whole-process acceleration processing from preprocessing, range profile reconstruction, feature extraction to intelligent identification is carried out on massive echo signals acquired by the millimeter wave radar, so that high-precision and high-real-time online detection and positioning of the heating surface pipe wall fine cracks are realized in a complex environment in a boiler with strong interference; finally, the detection efficiency is improved, meanwhile, the technical effect of high detection confidence is kept, and powerful technical support is provided for safe operation and preventive maintenance of the power plant boiler.

The invention discloses a real-time 3D reconstruction method, device and equipment based on a speckle image and a medium, and relates to the technical field of computer vision and three-dimensional reconstruction, the method makes full use of the large-scale parallel computing capability of a GPU, key steps such as stereo matching, parallax filtering and point cloud generation are efficiently executed in a video memory, and the real-time 3D reconstruction efficiency is improved. And the second-level or even millisecond-level 3D reconstruction response speed is realized. Compared with traditional CPU serial processing, the method has the advantages that data processing delay can be greatly reduced, continuous three-dimensional reconstruction of dynamic objects or real-time scenes is supported, and the space structure of the current moment can be displayed in real time. The technology effectively improves the timeliness and availability of 3D information acquisition, and can be widely applied to the fields of robot navigation, augmented reality, industrial detection, dynamic modeling and the like.

The application provides an AI multi-agent and digital twin fusion production scheduling process visualization method, medium and system, belonging to the technical field of AI multi-agent production scheduling. Large-scale parallel computing is realized by constructing a GPU three-layer CUDA processing architecture. The first layer of data preprocessing grid performs data cleaning in parallel. The second layer of negotiation analysis grid runs a Transformer-based agent interaction recognition model for parallel pattern recognition. The third layer of visualization calculation grid runs an LSTM-CNN fusion production scheduling process mapping model to generate visualization data. The multi-head attention mechanism dynamically adjusts the allocation of computing resources. The pipeline parallel and data parallel strategies optimize the computing performance. The asynchronous data transmission and computing overlap technology hides the memory access delay, solving the technical problem that multi-agent high-frequency negotiation data cannot be processed in real time.

The application discloses a bow sonar demonstration device based on a GPU parallel architecture, which mainly comprises a hardware system, a software system and a demonstration model, wherein the hardware system is used for completing a teaching task of simulating an operating sonar, wherein a GPU is used as a signal processing machine to provide large-scale parallel computing capacity and ensure real-time construction of a complex acoustic scene; the software system comprises signal processing software and display control software and is used for simulating teaching demonstration of basic sonar functions including noise warning, tracking, listening and feature analysis; and the demonstration model comprises one or more of a vector hydrophone model, a scalar hydrophone model, a sound base array model and a submarine model. The device realizes the visualization of abstract concepts of sonar equipment through three-dimensional dynamic visualization and real-time signal feedback.

This invention discloses an accelerated method and apparatus for precise probabilistic simulation in combinatorial equivalence checking, relating to the fields of electronic design automation (EDA) and high-performance computing. The method includes: parsing the input circuit combinational logic netlist to form an EPS operator graph and corresponding data distribution configuration, transmitting this data to a GPU; starting the GPU to distribute the EPS operator graph to a processing unit array for EPS calculation based on the data distribution configuration using a data flow-driven approach; and collecting the running status information of each round of calculation and feeding it back to the CPU for dynamic optimization of the next round of calculation. This method can transform circuit calculation tasks into data flow-driven EPS operator graphs and execute them on the GPU, efficiently utilizing the GPU's massively parallel computing capabilities to overcome performance bottlenecks. The pipelined task advancement based on superblocks and the dynamic optimization mechanism based on performance reports can adapt to the computational characteristics of different circuit structures, balance the load, optimize resource allocation, and significantly shorten the verification cycle of combinatorial equivalence checking.

The chip system, the data transmission method and the related equipment provided in the embodiments of the present application, the chip system comprises: an IO chip and a plurality of computing chips, each computing chip is configured with a corresponding chip hub, and each computing chip is connected with at least two physical interconnection ports in the IO chip through the chip hub; the chip hub comprises a splitting unit and a merging unit, the splitting unit is used for distributing the data stream sent by the computing chip to at least one physical interconnection port according to the service type; the merging unit is used for recombining or directionally forwarding the data stream received from the physical interconnection port to the computing chip, without modifying the external IO chip hardware specification, the data throughput rate and the overall transmission efficiency in the large-scale parallel computing scene are significantly improved.

The application provides a GPU fluid simulation method for real-time interactive application, and relates to the technical field of fluid simulation. The method first uses a particle system to emit a large number of particles, calculates fluid particle positions using a position-based fluid particle simulation algorithm, updates the motion state of the particles, then obtains a smooth fluid surface according to the particle positions through screen space processing, and finally uses a realistic rendering method to color the fluid surface to obtain a water body image. Since the state update of the large number of particles and the pixel-level calculation of the screen space are both large-scale parallel calculations, they are suitable for GPU processing, so all the calculation processes involved in the method are run on the GPU end. The method can be widely applied to various demand scenarios in the fields of industrial simulation and electronic games.

The application provides an AI accelerator processing optimization method, system, device and medium, and the method is applied to an AI accelerator in communication connection with a main memory. Through the collaborative architecture of the AI accelerator and the 3D DRAM, the application realizes reduction of transmission overhead and power consumption in the data carrying process, improvement of the computing throughput and the energy efficiency ratio, and simultaneously supports large-scale parallel computing tasks relying on the high bandwidth characteristics of the 3D DRAM.

The disclosure provides a kind of many-core cache consistency system, method, electronic equipment, storage medium and product, system is based on network-on-chip architecture, by introducing multiple nodes, corresponding router and the distributed directory deployed in router.Each node contains one or more processor cores and distributed last level cache, memory address is divided into multiple address blocks and is associated with distributed last level cache by dynamic address mapping rule. Distributed directory is used to record the state of cache line with distributed last level cache one by one, and the router is responsible for receiving and responding to requests from local or remote nodes, querying the distributed directory and updating the cache line state, which realizes efficient management of cache consistency.The technical scheme belongs to the field of communication technology, effectively solves the problem of high load and communication delay of master node in traditional cache consistency protocol, and improves the data consistency and access efficiency in multi-processor system and large-scale parallel computing environment.

The invention provides an inference task scheduling method and device, and the method comprises the steps: dividing an inference task into a plurality of subtasks based on an algorithm structure of an algorithm needed for executing the inference task; marking hardware execution information for each subtask based on the operation attribute of each subtask; the hardware execution information is used for indicating that the subtasks are executed by a control flow processing unit or a data flow processing unit in the network-on-chip; and distributing each sub-task to the control flow processing unit or the data flow processing unit for execution based on the execution sequence of each sub-task and hardware execution information. After a reasoning task is divided into a plurality of sub-tasks, the sub-tasks are mapped to the most appropriate heterogeneous hardware unit based on the operation attributes of the sub-tasks, so that the advantages of a control flow processing unit on logic control and the advantages of a data flow processing unit on large-scale parallel computing are fully exerted; therefore, the processing efficiency of the whole reasoning task is remarkably improved.

This invention provides a scalable hardware accelerator for neural networks based on FPGA, comprising a storage module, a computing module, and a control module. The storage module includes a preset parameter storage area and an intermediate feature map storage area. The preset parameter storage area stores convolutional weight parameters, bias parameters, and computation instruction sequences. The intermediate feature map storage area stores feature map data generated by each layer of the neural network, employing a multi-bank parallel feature map storage structure to achieve parallel access to intermediate feature map data through the collaborative work of multiple banks. The computing module includes a large-scale parallel computing unit array for convolutional neural network computation, achieving high-speed execution of convolution operations through the collaborative work of multiple parallel computing units. The control module performs timing control on convolutional kernel loading, bias loading, feature map reading, and computation instruction sequence execution. This invention improves computational efficiency while enhancing the system's flexibility and scalability.

The invention provides a three-dimensional-to-two-dimensional rendering method and system, electronic equipment and a storage medium, and the method comprises the steps: firstly receiving original three-dimensional scene data, carrying out the asynchronous and parallel preprocessing of the original three-dimensional scene data, and generating standardized data; and then carrying out synchronous and parallel data conversion processing on the standardized data by a plurality of rendering channels to generate a plurality of intermediate result images, so that the large-scale parallel computing capability of image processing equipment is fully utilized, the processing efficiency is improved, and the stability of color and light and shadow effects is improved. And finally, performing weighted mixing and synthesis processing on the plurality of intermediate result images to generate a corresponding two-dimensional image, thereby avoiding the problem that real-time feedback cannot be realized due to the fact that a complete rendering pipeline needs to be executed again during parameter adjustment, and ensuring that the rendering effect achieves the effect of what you see is what you get. Therefore, the effect stability of three-dimensional to two-dimensional rendering can be ensured, resource waste can be avoided, the time cost is effectively saved, and the rendering efficiency is improved.

The invention provides a processing optimization method, system and device of an AI accelerator and a medium. The method is applied to the AI accelerator in communication connection with a main memory. Through the collaborative architecture of the AI accelerator and the 3D DRAM, the transmission overhead and power consumption in the data carrying process are reduced, the computing throughput and the energy efficiency ratio are improved, and meanwhile large-scale parallel computing tasks are supported by means of the high-bandwidth characteristic of the 3D DRAM.

The invention relates to a transient electromagnetic arbitrary waveform three-dimensional forward modeling method and device and computer equipment. The method comprises the following steps: decomposing an emission source into a plurality of independent sources, adaptively constructing a local grid of each receiving point according to skin depth information of each time channel, and forming a minimum observation unit on a single time channel by a single independent source and a single local grid; determining a characteristic step length of a corresponding time channel according to the skin depth information, and calculating an electromagnetic field response result on a minimum observation unit; electromagnetic field response results of the multiple minimum observation units are subjected to parallel calculation, and a complete transient electromagnetic arbitrary waveform three-dimensional forward modeling result is obtained through synthesis. According to the method, a complete parallelization calculation framework is realized, the calculation load is greatly reduced while the numerical precision is maintained, the broadband transient electromagnetic efficient forward modeling simulation is possible in a large-scale parallel calculation environment, and a powerful technical support is provided for three-dimensional electromagnetic detection under a complex geological condition.

A hierarchical latch-tree memory architecture distributes and stores data values for massively parallel computing arrays without conventional SRAM or cache memory. Transparent latch circuits arranged as sequential tree levels propagate data on phase-shifted clock signals, providing local retention and eliminating read-write contention. Separate forward and reverse latch-tree networks broadcast activation data and collect output sums from processing elements. The latch hierarchy maintains balanced timing and extremely low energy per bit, supporting rack-scale computing throughput on the order of one zettaFLOPS (FP4 sparse AI inference) within practical power limits.

The invention relates to the technical field of computers, in particular to a video subtitle removal method, a chip, a GPU (Graphic Processing Unit) and electronic equipment, the method is executed on the GPU and comprises the following steps: receiving an input video and decoding the input video into a frame sequence; performing subtitle area detection on the current frame in the frame sequence, and generating a corresponding subtitle mask; in response to the subtitles existing in the current frame, predicting the content of the subtitle area according to the subtitle mask by using the spatial-temporal correlation of the previous frame and / or the subsequent frame in the frame sequence; and filling the predicted content into the caption region to generate a caption-removed video frame. According to the embodiment of the invention, a series of tasks such as video decoding, subtitle area detection, content prediction based on spatial-temporal correlation and final filling are deployed on the GPU, the large-scale parallel computing capability of the GPU is utilized to accelerate the processing flow, and the visual naturalness and the spatial-temporal coherence of the repaired video picture are improved.

This invention relates to the field of cloud computing resource management technology and discloses an AI-based dynamic scheduling and operation and maintenance system for large-scale data center computing resources. The system includes a kernel status monitoring module, a scheduling priority quantification module, a resource configuration retrieval module, and a synchronous clock scheduling execution module. It collects the system call trajectory of the task to be scheduled in the kernel state and the synchronous blocking state of the network protocol stack, extracts runtime characteristic data representing the execution phase, and calculates the scheduling urgency index by combining the topological weights of the task's directed acyclic graph. Then, it matches the target control group quota and writes the target control group quota into the resource limit parameter file when the task enters the communication waiting window. This invention locks the resource quota update action within the task's logical rest period, effectively eliminating the kernel state context switching overhead caused by computing power scheduling, ensuring the logical clock consistency of large-scale parallel computing tasks, and improving the global turnover efficiency of the resource pool.

The present invention is a method for calculating the energy deposition of a layout in proximity effect correction of large-scale parallel electron beam lithography. The purpose is to solve the memory and computing power bottlenecks of a single computer, expand the size limit of the layout to be calculated, and improve the calculation speed of the layout energy deposition, ultimately improving the efficiency of proximity effect correction of electron beam lithography, while ensuring accuracy. The present invention is divided into six steps: Step S1: Reading in the exposure layout and dividing it into sub-layouts; Step S2: Determining the edge regions of the sub-layouts; Step S3: Communicating between adjacent sub-layouts; Step S4: Calculating the energy deposition in large-scale parallel; Step S5: Developing and measuring the mean error; Step S6: Updating the exposure dose of the layout.

The invention belongs to the technical field of radar digital signal processing, and particularly relates to a GPGPU accelerated cancellation method for radar sidelobe interference based on an auxiliary channel. Aiming at the problem that an active array radar is easily influenced by sidelobe interference in a complex electromagnetic environment, the invention provides a sidelobe interference cancellation method based on an auxiliary channel structure, and efficient parallel acceleration is realized in combination with a GPGPU (General Purpose Graphics Processing Unit) so as to support real-time adaptive interference suppression of radar echo signals under multi-channel configuration. According to the method, the data dependency relationship of the multi-channel interference cancellation algorithm is deeply analyzed, the key calculation links are subjected to fine-grained parallel reconstruction, the large-scale parallel calculation potential of the GPGPU is fully excavated, and the processing throughput capacity is remarkably improved. Under the condition that GPGPU video memory resources are allowed, the method can be expanded to continuous interference suppression processing in a multi-pulse accumulation scene, and the real-time requirement of a modern radar system for continuous, stable and high-speed signal processing in a high-intensity interference environment is met.

The invention discloses a large-loop source transient electromagnetic fast forward modeling method based on GPU acceleration, and the method comprises the steps: firstly carrying out the parameter setting and preprocessing, then segmenting a large-loop source into a north edge, a south edge, an east edge and a west edge, and carrying out the discretization of each edge into N electric dipoles through employing a Gaussian-Legendre quadrature method; constructing a loop edge-frequency sampling point-wave number-time channel four-level parallel computing architecture to compute each edge; wherein each side in the GPU adopts a frequency-wave number-time parallel computing architecture, and parallel computing is performed on each electric dipole, so that the frequency-time domain response of each electric dipole is obtained; and finally, after calculation of all the electric dipoles is completed, vectorization calculation and summation are carried out on transient responses of all the electric dipoles on the GPU, a large loop source total field response at the current observation point is obtained, and a final time domain electromagnetic field value is output. According to the method, the advantages of large-scale parallel computing of the GPU can be efficiently and fully played, so that the computing efficiency is effectively improved on the premise of ensuring the computing precision.

The invention discloses a multispectral global remote sensing data-oriented color uniformizing method and a multispectral global remote sensing data-oriented color uniformizing system. The method comprises the following steps: firstly, constructing a global reflectivity reference base map, and then acquiring a corresponding position color-uniformizing base map according to a geographic position for global remote sensing data to be subjected to color uniformizing; thirdly, further segmenting the color-uniformizing base map and the data to be subjected to color uniformizing into a plurality of small image blocks with overlapped areas, and respectively calculating brightness characteristics of the small image blocks on the basis of tasseled cap transformation coefficients or equal weight transformation coefficients; adjusting the brightness distribution of the blocks of the image to be subjected to color homogenization according to the brightness characteristics and the one-dimensional histogram, adjusting all wave band values, and finally performing seam processing and re-splicing to obtain data with good color homogenization. According to the method, the color difference expansion phenomenon caused by a local color homogenizing method is effectively avoided, the influence of cloud layer coverage on the overall picture brightness can be avoided through picture blocking processing, the whole set of scheme is very suitable for large-scale parallel computing, and a reliable technical basis is provided for global high-resolution remote sensing image visualization and subsequent computing.

The invention discloses an electric leakage compensation method for a 2T0C in-memory calculation array, and belongs to the technical field of storage and calculation integration. A 2T0C main array and reference column driving mode is adopted, the compensation circuit is connected between the RBL of the 2T0C main array and the RBL of the reference column, the compensation circuit is used for dynamically adjusting the read voltage, calculation errors caused by the leakage effect can be effectively compensated, and IR-Drop is balanced by exerting symmetrical influence on calculation results of columns in the storage and calculation array. By adopting the method, stable calculation precision can be provided during large-scale parallel calculation, the system performance is remarkably improved, and the influence of a leakage effect on calculation accuracy is avoided.

The invention relates to a dual-decoupling parallel random number generator and a random computing system, which are characterized in that a unique dual-decoupling architecture is designed by adopting a basic architecture of a binary sampler, and the random number generator can be used for generating parallel random numbers on the basis of a dual-decoupling mechanism on the premise of not introducing complex generation logic and huge hardware overhead. High-quality and low-correlation random bit streams are generated through cooperative work of the random number generation core and the parallel comparison core. Due to the characteristics of low correlation and low cost, the method is particularly suitable for an SC system needing large-scale parallel computing, computing errors caused by correlation can be remarkably reduced, the contradictory requirements of simple hardware implementation, low expenditure and high-quality low-correlation bit stream generation are met, and the precision and reliability of the whole system are improved.