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Manufacturing method of stackable package structure

A manufacturing method and packaging structure technology, which can be used in semiconductor/solid-state device manufacturing, electrical components, electrical solid-state devices, etc., and can solve problems such as complex process and fragmentation.

Active Publication Date: 2013-11-20
ADVANCED SEMICON ENG INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0003] The manufacturing method of the known stacked package structure needs to be reposted to a different frame, which may cause fragmentation
In addition, after the wafer is cut, the die-to-die stacking is performed, which makes the overall process more complicated.

Method used

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  • Manufacturing method of stackable package structure
  • Manufacturing method of stackable package structure
  • Manufacturing method of stackable package structure

Examples

Experimental program
Comparison scheme
Effect test

Embodiment Construction

[0009] refer to Figures 1 to 18 , is a schematic diagram showing the first embodiment of the manufacturing method of the stacked package structure of the present invention. refer to figure 1 , providing a wafer 21 . The wafer 21 includes a first surface 211 , a second surface 212 and a plurality of holes 214 . In this embodiment, the wafer 21 is a silicon substrate, and the holes 214 are blind holes opening on the first surface 211 . In this embodiment, the first surface 211 is an active surface and includes some active components (not shown), and the second surface 212 is a back surface.

[0010] refer to figure 2 , forming an insulating material 221 (for example: polyimide (Polyimide, PI), epoxy resin (Epoxy), benzocyclobutene (Benzocyclobutene, BCB) and other non-conductive polymers or inorganic insulating materials, for example: two Silicon oxide (silicon dioxide (SiO 2 )) on the sidewalls of these holes 214, and define several central grooves. Afterwards, a condu...

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PUM

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Abstract

The invention relates to a manufacturing method for a stackable package structure. The manufacturing method comprises the following steps of: (a) arranging a first carrier on a first surface of a wafer, wherein the wafer comprises the first surface, a second surface and a plurality of conduction columns, and the second surface is opposite to the first surface; (b) arranging a second carrier on the second surface; (c) removing the first carrier; (d) arranging a plurality of crystalline grains on the first surface; (e) removing the second carrier; and (f) cutting the wafer to form the stackable package structure. By using the second carrier, a crystalline grain to wafer process can be performed, so that the process time is shortened, the process is simplified and the product yield is increased.

Description

technical field [0001] The present invention relates to a manufacturing method of a packaging structure, in particular, to a manufacturing method of a stacked packaging structure. Background technique [0002] It is known that a wafer with several conductive via structures is attached to a carrier on its active surface, so as to facilitate the completion of the backside structure of the wafer. Then, stick the back side of the wafer to a dicing tape of a frame to remove the carrier; then, transfer the active surface of the wafer to a dicing tape of another frame to cut the wafer into several first grain. Afterwards, disposing at least one first crystal grain on a substrate, and stacking second crystal grains on the first crystal grain to form composite crystal grains. Finally, at least one composite chip and the substrate are packaged to form a stack package structure. [0003] The known manufacturing method of the stacked package structure requires secondary transfer to a...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/50H01L21/56H01L21/60
CPCH01L2224/16225H01L2924/15311
Inventor 杨国宾萧伟民洪正辉
Owner ADVANCED SEMICON ENG INC