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Built-in test modeling simulation method based on state diagram

A simulation method and state diagram technology, applied in special data processing applications, instruments, electrical digital data processing, etc.

Inactive Publication Date: 2013-01-30
北京恒兴易康科技有限公司
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

In the current public information about BIT design and analysis methods, there is no method for BIT modeling and simulation analysis using state diagram technology

Method used

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  • Built-in test modeling simulation method based on state diagram
  • Built-in test modeling simulation method based on state diagram
  • Built-in test modeling simulation method based on state diagram

Examples

Experimental program
Comparison scheme
Effect test

Embodiment

[0184] The method of the present invention will be described below by taking the CPU board and the BIT of the central alarm computer of a certain equipment integrated avionics system as an example.

[0185] The CPU board BIT state diagram simulation comprehensive model is composed of 4 modules: UUT, interference, test BIT, integrated management BIT, several fault modes selected in the case, and their normal values, fault values ​​and fault codes, as shown in Table 11 .

[0186] Table 11 Case Failure Modes

[0187]

[0188] Step 1: Establish a state diagram model of the CPU board

[0189] (1) Input of CPU board state diagram model

[0190] The input of the CPU board state diagram model is shown in Table 12.

[0191] Table 12 Input of CPU board state diagram model

[0192]

[0193] (2) Output of CPU board state diagram model

[0194] The output of the CPU board state diagram model is shown in Table 13.

[0195] Table 13 Output of CPU board state diagram model

[019...

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PUM

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Abstract

The invention discloses a built-in test (BIT) modeling simulation method based on a state diagram, belonging to the technical field of test of electronic information. The method comprises the following steps of: step 1, establishing a state diagram model of a tested unit; step 2, establishing a state diagram model of the BIT; step 3, establishing a state diagram model of interference; step 4, establishing a BIT simulation comprehensive model; step 5, performing fault and interference injection and simulation evaluation. The method provides a universal key element template of the BIT based on design characteristics of the BIT, and BIT key element decomposition can be quickly performed according to the template; and the method provides basic modes for state diagram modeling of each element in the BIT, and can perform modeling on common analogue BIT, digital BIT and software BIT. The invention provides a simulative injection method for the fault and the interference, and fault detection and false alarm suppression capability of the BIT can be analyzed through state simulation.

Description

technical field [0001] The invention belongs to the technical field of testability of electronic information, and relates to a modeling and simulation method of a built-in test (BIT) using state chart technology. Background technique [0002] Built-in test (Built-In Test, BIT) is the automatic test capability provided by the system or equipment to detect and isolate faults. It is an important part of electronic systems or equipment. BIT is a powerful means to improve system fault diagnosis and maintenance capabilities. Greatly reduce equipment maintenance and comprehensive support costs. At present, BIT is developing from analog to digital, from hardware to software and the direction of integration of hardware and software. [0003] In the existing BIT design analysis methods, in addition to the engineering design analysis method, it also includes modeling and analysis of the relationship between faults and BIT based on TEAMS software, and BIT circuit performance modeling a...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F17/50
Inventor 石君友李海伟王璐
Owner 北京恒兴易康科技有限公司
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