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Storage method with cumulative write-in characteristic, storage device and storage system

A technology of memory and storage unit, which is applied in the field of memory and storage systems to reduce workload and avoid conversion delay

Active Publication Date: 2013-07-24
XI AN UNIIC SEMICON CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0027] However, when the OR operation or AND operation data is stored in the cache memory, although the faster cache memory shortens the delay time, the above-mentioned method cannot completely solve the aforementioned series of problems

Method used

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  • Storage method with cumulative write-in characteristic, storage device and storage system
  • Storage method with cumulative write-in characteristic, storage device and storage system
  • Storage method with cumulative write-in characteristic, storage device and storage system

Examples

Experimental program
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Embodiment Construction

[0061] figure 1 A typical 6-transistor SRAM cell with two cross-coupled inverters (inverters) and two data switches (transistors). Through the data switch, the unit can connect the normal phase data and reverse phase data to the normal phase data transmission line and the reverse phase data transmission line respectively (this figure only shows the write path).

[0062] If a general write command is issued, the access line will activate the SRAM cell that matches the address. The data is transferred from the data transmission line (the transmission line is shared by multiple units, only one unit in this diagram) to the cross-coupled inverter through the data switch. This will overwrite and overwrite previously stored information within the SRAM cell.

[0063] The circuit structure of the SRAM unit that can execute the "write_or" instruction in the present invention can be found in figure 2 with image 3 , the modified instruction-decoder (ie, decoder) can decode the "writ...

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Abstract

Provided are a storing method, a memory, and a storing system characterized by accumulated data-writing. OR-operations and AND-operations are transferred from a CPU / ALU to inside of a memory so as to reduce the number of times that data transmission lines switch between read and write. An interface unit of the memory comprises a write operation instruction interface, a write instruction interface, and an address instruction interface; the write operation instruction interface comprises a "write_or" instruction interface and / or a "write_and" instruction interface; an instruction / address decoder is used to decode write operation instructions, write instructions, and address instructions; the drive capability of a p field-effect transistor is greater than the drive capability of a data switch, and the drive capability of an n field-effect transistor is smaller than the drive capability of a data switch. The storing method, memory, and storing system reduce the workload of a CPU / ALU, and enable continuous data-writing into a memory.

Description

technical field [0001] The invention relates to a data storage method used in electronic equipment and a corresponding memory and storage system. Background technique [0002] Different types of memory such as dynamic random access memory (DRAM), static random access memory (SRAM), and flash memory (Flash) have been used in almost all modern electronic devices (computers, mobile phones, routers, set-top boxes, printers, global positioning systems (GPS) etc.). These memories can be used to store and retrieve binary digital data, and to process this data by different parts of the system itself, such as the central processing unit (CPU). [0003] For writing to the memory, the memory will give an address and a write command. At the same time as or after the write command is given, the data will be given, and the data will be written to the memory unit of the selected address (according to the type of memory device used, it will be in a single cycle in a single pin or in paral...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G11C11/4197G11C16/06
CPCG06F9/3001G06F9/30145G11C11/419G11C16/06H01L27/12
Inventor 郝亨福
Owner XI AN UNIIC SEMICON CO LTD