Method of flattening the substrate

[0054] Many different embodiments or examples are provided below to implement the features of various embodiments of the present invention. The following will briefly describe the structure and arrangement of specific embodiments. Of course, the following description is only an example and is not intended to limit the present invention. In addition, in each example of the present invention, there may be repeated element numbers, but the above repetition is only used to briefly and clearly describe the present invention, and does not mean that the various embodiments and structures are related.

[0055] Chemical mechanical polishing (CMP) is a process used to remove the film from the surface of the substrate, and it is usually used to remove the undulating film on the surface of the substrate. Since the chemical mechanical polishing pad presses the entire substrate surface, this process can remove the surface undulations across the entire substrate. Chemical mechanical polishing can be used to remove various types of thin films, such as polysilicon, oxides, and metals. However, in some applications, chemical mechanical polishing can cause unevenness within wafer (WIW) or within die (WID), which affects the photolithography process for forming small components.

[0056] Figure 1A The semiconductor device region 100 on the substrate 101 in some embodiments of the present invention is shown. In some embodiments, the substrate 101 is a semiconductor substrate (or semiconductor wafer). The semiconductor substrate 101 may include elemental semiconductors, including silicon or germanium with crystalline, polycrystalline, or amorphous structures; compound semiconductors, including silicon carbide, gallium arsenide, gallium phosphide, iodine phosphide, iodine arsenide, and iodine antimonide; Alloy semiconductors, including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and GaInP; any other suitable materials; and/or combinations of the above. In some embodiments, the alloy semiconductor substrate may have a gradient SiGe pattern, and the Si and Ge composition of the gradient SiGe pattern varies from one ratio at one location to another ratio at another location. In some other embodiments, the SiGe alloy is formed on the silicon substrate. In some other embodiments, the SiGe substrate is strained. In addition, in some embodiments, the semiconductor substrate may be a semiconductor on insulator (SOI for short) or a thin film transistor (TFT). In some examples, the semiconductor substrate may include a doped epitaxial layer or a buried layer. In some other examples, the compound semiconductor substrate may have a multilayer structure, or the silicon substrate may include a multilayer compound semiconductor structure. In another example, the substrate 101 may be a non-semiconductor material, such as a glass substrate.

[0057] Shallow trenches 102 and 103 are formed on the substrate 101, which can be formed by etching and patterning a first dielectric layer 112 and a second dielectric layer 114. The film layers 112 and 114 can be formed by a deposition process, such as chemical vapor deposition (chemical vapor deposition, hereinafter referred to as CVD), plasma enhanced chemical vapor deposition (hereinafter referred to as PECVD), and thermal chemical vapor deposition. Deposition method (thermal CVD), high density plasma chemical vapor deposition (high density plasma CVD, referred to as HDCVD) or spin coating process. In this embodiment, other suitable processes can be used. In one example, the step of forming the first dielectric layer 112 may include growing a pad oxide layer on the semiconductor substrate 101. In addition, the film layers 112 and 114 may include any suitable composition and/or thickness. The second dielectric layer 114 may include a nitrogen-containing material, such as silicon nitride and/or silicon oxynitride; amorphous carbon material; silicon carbide; other suitable materials and/or the aforementioned composition. In this embodiment, the second dielectric layer 114 includes a silicon nitride layer. It is understood that the film layers 112 and 114 may include a single layer or multiple layers. In addition, in some embodiments, the semiconductor device region 100 can completely omit the first dielectric layer 112 or the second dielectric layer 114.

[0058] In some embodiments, after the trenches 102 and 103 are formed, the opening is lined with a liner 120 and a filling layer 122. The liner 120 may be formed on the trenches 102 and 103 by any suitable process. For example, the step of forming the liner 120 may include growing a thermally oxidized trench liner to improve the interface of the trench. In some embodiments, the liner 120 in the semiconductor region 100 may be completely omitted. The filling layer 122 deposited on the semiconductor substrate 101 fills the trench. In some embodiments, the filling layer 122 includes a dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, fluoride-doped silicate glass (FSG), low dielectric constant materials, and other suitable materials. The materials and/or combinations of the above. In addition, the filling layer 122 can be formed by any suitable deposition process, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), sputtering, electroplating, high-density plasma (high-density plasma) density plasma, HDP for short), high aspect ratio deposition process (HARP), other suitable methods, and/or combinations of the above. In some embodiments, the trench is filled with chemical vapor deposition (CVD) oxide.

[0059] After that, please refer to Figure 1B A chemical mechanical polishing process is performed on the filling layer 122 to etch back and planarize the filling layer 122 until the second dielectric layer 114 (that is, the silicon nitride layer in this embodiment) is reached and exposed. The chemical mechanical polishing process can be selectively stopped on the second dielectric layer 114 to complete the fabrication of shallow trench isolations (STIs) 132, 133. The shallow trench isolation includes a liner 120 and a filling layer 122, leaving the shallow Trench isolation has a step height (step height) or thickness (T1 and T2), such as Figure 1B Shown. Due to variations in the chemical mechanical polishing process, the thickness of the filling layer 122 (such as T1 and T2) in the trenches across the substrate (variation of WIW in the wafer) and across the die (variation of WID in the die) may be different. the same. Figure 1C It is shown that in some embodiments, on part of the substrate (or wafer), the chemical mechanical polishing process can make the filling layer 122 protrude above the second dielectric layer 114, and the resulting thickness (T H ) Is relatively larger than the target thickness (for example, when the chemical mechanical polishing process stops at the thickness of the second dielectric layer). In contrast, in some other embodiments, such as Figure 1D As shown, on other parts of the substrate, the chemical mechanical polishing process can make the filling layer 122 recessed under the second dielectric layer 114, and the resulting thickness (T L ) Is relatively smaller than the target thickness.

[0060] The Dish Effect of the chemical mechanical polishing process can also change the height of the filling layer 122 in the trench. in Figure 1B Among them, the shallow trench isolation structure 133 is much wider than the shallow trench isolation structure 132, and the disk effect of the chemical mechanical polishing process makes the filling layer of the shallow trench isolation structure 133 lower than the surface by a depth D 2 , Making the filling layer 122 of the shallow trench isolation structure 132 lower than the surface by a depth D 1 , D 2 Greater than D 1. The thickness of the different filling layer 122 (such as Figure 1B , Figure 1C with Figure 1D (Shown) and the amount of disks with different grooves produce an asynchronous step height across the substrate on the substrate, which will reduce the quality of the patterning (such as the patterning of the gate structure) lithography process.

[0061] In addition, in some embodiments, such as Figure 1E As shown, the filling thickness of different trenches on the substrate will result in the replacement gate (RPG) formed with different heights. Figure 1E Three exemplary gate structures 141, 142, and 143 on the substrate 101 are shown. Such as Figure 1E As shown, in some embodiments, since the aforementioned gate is disposed on an uneven surface, the gate structure 141 (H 2 ), 142(H 1 ) And 143 (H 3 ) Are not the same height. In some embodiments, the gate structure includes a gate dielectric layer 150, a dummy polysilicon layer 155 and a nitride spacer 153. In some embodiments, the gate structure includes other materials and/or films. After the gate structure is formed, an etch stop layer (ESL) and an interlayer dielectric (interlayer dielectric, 126) may be formed on the substrate 101 (including at least one gate structure) by any suitable process. Referred to as ILD). The etch stop layer (ESL) may include silicon nitride, silicon oxynitride, and/or other suitable materials. The composition of the etch stop layer (ESL) can be selected according to the etch selectivity for one or more additional patterns of the device region 100. In this embodiment, the etch stop layer (ESL) is a contact etch stop layer (CESL). The interlayer dielectric layer 126 (ILD) may include silicon nitride or a low dielectric constant material. In some embodiments, the interlayer dielectric layer includes high density plasma (HDP) oxide. In other embodiments, the interlayer dielectric layer 126 may optionally include spin-on-glass (SOG) or high aspect ratio (HARP) oxide.

[0062] Such as Figure 1F As shown, in some embodiments, a chemical mechanical polishing process is used to planarize the interlayer dielectric layer 126 (ILD) until the top of at least one gate structure (eg, gate structure 141, 142, or 143) on the semiconductor substrate 101 is exposed. Since the gate structures (such as the gate structures 141, 142, and 143) have different heights, some interlayer dielectric layer 126 (ILD) may be left above the dummy polysilicon layer. Such as Figure 1F As shown, there is an interlayer dielectric layer 126 (ILD) with a thickness of "L" above the gate structure 143. For the gate replacement process, the dummy polysilicon layer 155 needs to be etched away and replaced with other materials (such as metal materials and/or work function materials). The remaining interlayer dielectric layer 126 (ILD) above the gate structure 143 prevents the dummy polysilicon layer 155 in the gate structure 143 from being removed (for example, removed by an etching process), thereby affecting the yield of the device. Above Figure 1A~1F The embodiment of the disclosure reveals the problems caused by unevenness and unevenness of the chemical mechanical polishing process.

[0063] Gas cluster ion beams (GCIBs) are cluster ion beams and can be used to remove (or etch) thin films on the substrate surface. Gas clusters are nano-sized aggregated materials that are gaseous under standard conditions and elevated temperatures and pressures. When a gaseous material is released into the vacuum chamber as a jet, the static enthalpy is exchanged with kinetic energy, and the jet cools. The above-mentioned cooling is due to the expansion of the jet in a vacuum state. Part of the ejecta rapidly cools and condenses, forming gas clusters. The gas clusters can be ionized by ion bombardment, so that the gas clusters form a guided beam with controllable energy. The ionized gas clusters can also be accelerated to achieve the required kinetic energy.

[0064] Larger size ion clusters are usually the most useful, because the unit ion cluster can carry a larger energy, while the unit molecule has a lower energy, and the ion cluster will impact the substrate. The individual molecules of a particular ion cluster only carry a small proportion of the total cluster energy. Therefore, the impact effect of larger ion clusters will generally affect (but not be limited to) very shallow surface areas. This allows gas cluster ions to be applied to various surface adjustments, such as etching, but unlike other ion beam processes, they tend to produce deeper surface damage. For an example of the gas cluster ion beam device, please refer to US Patent Publication No. "2009/0087578" filed on September 29, 2007, which is titled "Method for depositing films using gas cluster ion beam processing".

[0065] Please refer to Figure 2A By releasing a gaseous precursor, a gas cluster 205 is formed, which, in some embodiments, can remove silica in the vacuum chamber. In some embodiments, the gas precursor may include an etching gas (such as NF) used to remove dielectric films (such as oxides, nitrides, oxynitrides, or silicon-containing films, such as polysilicon). 3 And CF 4 ). Other suitable gas precursors can be (or include, but are not limited to) carbides, fluorine-containing gases (such as C x F y Or C m H n F o ), halide (e.g. HBr), SF 6 , C 12 Or HF. In some embodiments, the gas precursor may also include an etching assist gas, such as O 2 , N 2 , Or NH 3. In addition, in some embodiments, the gas precursor also includes a carrier gas (or dilution gas or passivation gas) such as Ar or He. The gas precursor may further include one or more doping gases, such as B 2 H 6 , PH 3 , AsH 3 Or GeH 4. Gases available in other forms can also be used as gas precursors for gas cluster ion beams.

[0066] In some embodiments, clusters can be ionized or filtered, and move substantially along a direction 202 perpendicular to the substrate surface 201. In some embodiments, such as Figure 2A As shown, the ion clusters can also be accelerated by an electric field to obtain the required kinetic energy, and when the ion clusters hit the substrate surface 201, they can be separated into gaseous substances, such as molecules or charged molecules.

[0067] In some embodiments, the gas may be a mixture of two or more types of gases that do not react at room temperature or lower (for example, 15°C to 200°C). In some embodiments, the gas precursor includes NF 3 gas. When the ion clusters of the mixed gas hit the surface of the substrate, the kinetic energy of the ion clusters is converted to thermal energy, which will cause a very high local temperature (for example, greater than 400°C), causing the mixed gas to react to form a metal film, and the remaining gaseous substances will leave The surface of the substrate.

[0068] In some embodiments, ion clusters may contain a small number or thousands of molecules. In some embodiments, the kinetic energy of the ion cluster may range from about 1 keV to tens of keV (for example, 90 keV). In some other embodiments, the kinetic energy of the ion cluster may range from about 20 keV to 60 keV. After the ion clusters hit the substrate surface 201 (for example, at point A), the kinetic energy is converted to heat energy that generates a local high temperature, helping to release (or drive) unreacted gas species and reacted gas species on the substrate surface. The reactive gas species refer to the etching byproducts of the etching gas precursor and the surface film. In some embodiments, the time of impact is very short, such as only a few trillionths of a second. Due to the short impact time, the kinetic energy range of the ion clusters is not large, and the depth of the surface layer of the substrate 200 affected is very shallow, for example, between about 1 nm and about 50 nm. Although the instantaneous local temperature (close to the impact point A) is very high when the impact occurs, because the impact time is very short, the temperature of the substrate (or the entire substrate) will not change. In some embodiments, the local temperature at location A is between about 700°C and about 1000°C.

[0069] Gas cluster ion beam (GCIB) can be used to etch (or remove) materials and planarize uneven surfaces. The surface layer after gas cluster ion beam (GCIB) etching will become somewhat different from the underlying substrate body. Figure 2B The surface profile of the substrate 210 with the film 215 (as indicated by the curve 250) is shown in some embodiments. In some embodiments, the surface profile can be measured with a surface profile measuring instrument (for example, Atomic Force Microscopy, AFM or Surface Roughness Meter). In some embodiments, the film thickness of the surface film on the substrate can also be measured. In some embodiments, the measured profile image (including thickness data) is provided to a gas cluster ion beam (GCIB) device to remove highly undulating surface areas, such as Figure 2B Shown. In some embodiments, in addition to removing the surface profile, a gas cluster ion beam (GCIB) can be used to remove the additional film thickness "C", so that the film 215 has a target thickness "D", such as Figure 2B Shown. As described above, the gas cluster ion beam (GCIB) can cause damage to the top surface, however, the damaged surface is very shallow (for example, the thickness is about 1 nm-50 nm). In some embodiments, a wet etching process may be used to remove the damaged surface, such as a buffer oxide etch (BOE) to remove the oxide layer.

[0070] Table 1 shows the uniformity data of an exemplary surface, where the surface was deposited with about 3,600 angstroms of phosphorous-doped glass (PSG) oxide and removed by etching using gas cluster ion beam (GCIB) About 1,000 angstroms of PSG to reduce the surface profile, and after the use of gas cluster ion beam (GCIB) etching to remove the surface layer (which may cause damage to the surface layer), a short-time buffer oxide etching (BOE) is performed.

[0071] After depositing the film

[0072] Table 1 shows the comparison of uniformity data for a substrate after each process.

[0073] The data in Table 1 shows that after PSG deposition, the 3 sigma (3σ) thickness percentage is a bit high at 6.8% (or +/- 24.1 nm). An optical measuring instrument (such as SFX-100 manufactured by KLA-Tencor located in Milpitas, California) can be used to obtain substrate surface uniformity data. After that, the substrate surface profile data (including thickness information and corresponding coordinates) are provided to the gas cluster ion beam (GCIB) system. The gas cluster ion beam (GCIB) system will distinguish the position and the thickness of the substrate based on the provided information. The film needs to be removed. The data in Table 1 shows that after the gas cluster ion beam (GCIB) etching process, the thickness uniformity (3 sigma) is reduced to 1.7% (or +/-4.5nm). As described above, gas cluster ion beam (GCIB) etching may leave a damaged surface layer, for example, a part with a thickness of about 1 nm to 50 nm. The damaged layer can be removed using wet etching. After the gas cluster ion beam (GCIB) etching, the substrate undergoes a short-time buffer oxide etching (BOE), and the thickness uniformity is measured. The data shows that the uniformity is approximately the same as that after gas cluster ion beam (GCIB) etching, which means that the gas cluster ion beam (GCIB) etching does not cause unevenness on the substrate surface. In some embodiments, the required flatness (3 sigma required) is approximately less than +/-50 Angstroms. 3 Sigma surface flatness of 4.5nm (or +/-45 angstroms) can meet the demand.

[0074] In addition to blank wafers, gas cluster ion beam (GCIB) etching can also be performed on the patterned substrate to verify that it can improve flatness on the patterned substrate. Table 2 shows the film uniformity of an exemplary patterned substrate, the substrate is deposited with an oxide film and processed by gas cluster ion beam (GCIB) etching. The thickness of the deposited film is about 3,500 angstroms. The 2,500 angstrom part of the deposited film is removed by chemical mechanical polishing. Gas cluster ion beam (GCIB) etching removes the film with a thickness of about 500 angstroms after chemical mechanical polishing. .

[0075] After depositing the film

[0076] Table 2 shows the comparison of uniformity data of a patterned substrate after deposition and after gas cluster ion beam (GCIB) etching.

[0077] The data in Table 2 shows that the thickness range of 3 sigma is a bit high (approximately 17.1 nm) after phosphorus-doped silica glass (PSG) is deposited. After obtaining the substrate surface profile information, the substrate surface profile information (including thickness and coordinates) is provided to the gas cluster ion beam (GCIB) system to remove the oxide film on the substrate. The 3 sigma variation after etching is reduced to 4.2 nm, which shows that gas cluster ion beam (GCIB) can be used to improve the uniformity on the patterned substrate. In some embodiments, the flatness requirement is about less than +/-50 angstroms. In this example, the 3 sigma surface flatness is 4.2 nm (or +/- 42 angstroms), which can meet the above requirements.

[0078] The experimental data shown and described in Table 1 and Table 2 above show that gas cluster ion beam (GCIB) etching can be used to improve the flatness of blank and patterned substrates. In some embodiments, for the above Figure 1A The shallow trench isolation structure described can be subjected to a chemical mechanical polishing process to grind a part of the filling layer 122 and leave a part of the filling layer 122 with a thickness of "M" on the substrate, such as Figure 3A Shown. In some embodiments, the chemical mechanical polishing process stops before the chemical mechanical polishing contacts the second dielectric layer 114. In some other embodiments, when the chemical mechanical polishing pad starts to contact the second dielectric layer 114, the chemical mechanical polishing process stops. After the chemical mechanical polishing process is stopped, the contour and thickness of the substrate are measured. In some embodiments, only in-wafer (WIW) uniformity data is collected. In some other embodiments, both in-wafer (WIW) and in-die (WID) data are collected. The more in-wafer (WIW) and in-die (WID) data are collected, and after the gas cluster ion beam (GCIB) is planarized, a more uniform substrate can be obtained. However, collecting additional data requires additional time.

[0079] Figure 3B It shows some substrates 101 etched by gas cluster ion beam (GCIB) of the present invention. Figure 3B It is shown that due to the precise etching with gas cluster ion beam (GCIB) and supplemented by contour and thickness images (or data), the filling layer 122 can be flattened to obtain a much better uniformity, and there will be no dishing, and There will be no over or under grinding. Since chemical mechanical polishing has good output, initial polishing of the oxide layer by chemical mechanical polishing can increase the output. The final treatment of the remaining oxide with a gas cluster ion beam (GCIB) can improve the thickness uniformity in the wafer (WIW) and in the die (WID).

[0080] In addition to improving flatness, gas cluster ion beam (GCIB) etching can also obtain the exact position of the etching or polishing end point. As mentioned above, the unevenness of chemical mechanical polishing can lead to shallow dishes, over-grinding and/or under-grinding. With the help of thickness measurement data or images, gas cluster ion beam (GCIB) etching can be adjusted to partially remove the required film thickness to achieve a flatness that can meet specifications. In some embodiments, multiple thickness and/or profile measurements can be performed between multiple gas cluster ion beam (GCIB) etchings to achieve the final and required film removal. With multiple thickness and/or profile measurements and gas cluster ion beam (GCIB) etching, optimal flatness across the wafer and die can be obtained. In some embodiments, a 3 sigma thickness variation of less than 25 angstroms can be achieved. However, multiple measurements and multiple gas cluster ion beam (GCIB) etching will slow down the process and increase manufacturing costs.

[0081] Figure 3C A process flow diagram 350 of forming a shallow trench isolation structure on a substrate is shown in some embodiments of the present invention. In step 351, a substrate with a hard mask layer is etched to form a trench. As mentioned above, there may be one or more dielectric layers on the substrate, and the dielectric layer is patterned and used as a hard mask layer for etching trenches. In some embodiments, step 353 is performed to deposit a filling layer after etching the trench. As above Figure 1A As described, the filling layer is composed of a dielectric material. In some embodiments, before depositing the filling layer, a liner layer is deposited to line the sidewalls of the trench.

[0082] After that, in step 355, a chemical mechanical polishing process is performed to remove part of the filling layer, and to planarize the substrate comprehensively. In some embodiments, the chemical mechanical polishing process stops before contacting the hard mask layer. In some other embodiments, the chemical mechanical polishing process stops when it starts to contact the hard mask layer. In at least one embodiment, the hard mask layer is also used as a chemical mechanical polishing stop layer. Subsequently, step 356 is performed to measure the surface profile and film thickness of the substrate, and this measurement spans the entire substrate. In some embodiments, in addition to the data in the wafer, the data in the die is also collected, and the coordinates of the data are collected. After collecting the data, the data is provided to a gas cluster ion beam (GCIB) etching device. In step 357, a gas cluster ion beam (GCIB) etching is performed on the substrate to remove the filling layer on the trench, so as to achieve planarization through the data collected in step 356, and make the gas cluster ion beam (GCIB) etching device Decide how many layers to remove at different locations on the substrate.

[0083] In some embodiments, after the gas cluster ion beam (GCIB) etching step 357, the step 358 of measuring the contour on the substrate and the thickness of the filling layer is performed again as needed. Step 358 is to check whether the flatness of the substrate meets the standard, and also check whether there is a filling layer outside the trench to be removed. If the flatness does not meet the target and/or there is still a filling layer outside the trench, step 359 may be performed as needed to remove the excess filling layer on the substrate and achieve the target flatness.

[0084] Steps 358 and 359 can be repeated until the desired result is achieved. In some embodiments, after the gas cluster ion beam (GCIB) etching is completed, a wet etching process is performed in step 360 to remove the damaged film layer on the substrate surface. Since the damaged film is very shallow, the wet etching takes a very short time. In some embodiments, the wet etching takes about 5 seconds to 5 minutes. Some embodiments of the present invention do not perform step 360.

[0085] The aforementioned use of bulk cluster ion beam (GCIB) etching to improve flatness and/or perform final film removal is not only used to remove the shallow trench isolation filling layer. This mechanism can also be used in other planarization operations to achieve planarization and film removal. Figure 4A A cross-sectional view of the device region 400 including two gate structures 401a and 401b is shown in some embodiments of the present invention. The element area 400 is provided on the substrate 405. The gate structures 401a, 401b have two gate stacks 403a, 403b, respectively. In some embodiments, each gate stack 403a, 403b has a multilayer structure in the stack. For example, the gate stacks 403a, 403b may include a gate dielectric layer 430, which may be a silicon oxide layer, a silicon oxynitride composite layer, a high-k dielectric layer, or a high-k dielectric layer above the oxide layer. The gate stacks 403a, 403b also include a dummy gate layer 435, which is composed of a conductive material such as polysilicon. The gate stacks 403a and 403b may also include other layers, such as a barrier layer and/or a work function layer (not shown) used to replace the gate.

[0086] In some embodiments, the gate stacks 403 a and 403 b are patterned with a double-layer hard mask, which includes a first hard mask layer 411 on the second hard mask layer 412. Both the first and second hard mask layers are composed of dielectric materials. In some embodiments, the first hard mask layer 411 is composed of oxide, and the second hard mask layer 412 is composed of nitride or oxynitride. The film layers 411 and 412 can be formed by deposition processes, such as chemical vapor deposition (CVD), spin coating process, high aspect ratio process (HARP), chemical vapor deposition including plasma assisted chemical vapor deposition (PECVD), thermal chemical vapor deposition ( thermal CVD), high density plasma chemical vapor deposition (HDPCVD), etc. This embodiment can also use other applicable processes. In some embodiments, since the gate width (or length) “Wa” of the gate stack 403a is significantly wider than the gate width (or length) “Wb” of the gate stack 403b, the first hard mask layer 411 may be It is removed when the gate stack 403b is patterned, which is the result of protecting the first hard mask layer 411 by the undeveloped photoresist layer above the gate structure 403a.

[0087] The gate stacks 403a, 403b are surrounded by spacers 407, where spacers 407 are made of dielectric materials. Other film layers may exist between the gate stacks 403a, 403b and the spacer 407. In some embodiments, the gate stacks 403a, 403b are covered by an etch stop layer 408, wherein the etch stop layer 408 extends to the substrate surface not covered by the gate stacks 403a, 403b. An interlayer dielectric layer 410 (ILD) is disposed on top of the etch stop layer, and the interlayer dielectric layer can be deposited and formed by any suitable process. The top of the etch stop layer may include silicon nitride, silicon oxynitride, and/or other suitable materials. The composition of the etch stop layer (ESL) can be selected based on the etch selectivity for one or more additional patterns of the device region 400. In this embodiment, the etch stop layer (ESL) is a contact etch stop layer (CESL). The interlayer dielectric layer 410 (ILD) may include silicon nitride or a low dielectric constant material. In some embodiments, the interlayer dielectric layer 410 includes high density plasma (HDP) oxide. In other embodiments, the interlayer dielectric layer may optionally include spin-on-glass (SOG) or high aspect ratio (HARP) oxide.

[0088] In some embodiments, the interlayer dielectric layer 410 is planarized by one or more chemical mechanical polishing processes until the dummy gate layer 435 is exposed. As described above, since the width (or length) "Wa" of the gate structure 401a is wider than the width (or length) "Wb" of the gate structure 401b, the first hard mask layer 411 remains on the gate stack 403a without Remain on the gate stack 403b. In addition, the chemical mechanical polishing process polishes the interlayer dielectric layer 410 above the narrow structure 403b faster than the interlayer dielectric layer above the wider structure 403a. Therefore, the dielectric layer above the dummy gate layer 435 of the narrow gate structure 403b is completely removed before the dielectric layer above the gate structure 403a. It is a challenge to use a chemical mechanical polishing process to remove films on the surface of substrates with varying widths (or structural dimensions) and different material layers.

[0089] In some embodiments, in order to achieve the removal of the dielectric layers on the dummy gate layer 435 with the gate structure of varying width and length, a part of the interlayer dielectric layer 410 is removed as shown in 4B. The chemical mechanical polishing process removes large-scale surface contours and improves flatness. However, the chemical mechanical polishing process still leaves some in-wafer (WIW) and die (WID) inhomogeneities. Figure 4B It is shown that the remaining layer 410 on the gate structure 401b is thinner than the remaining layer on the wide gate structure 401a. This is because the chemical mechanical polishing process removes the film faster near the narrower and isolated structures. In some embodiments, a thin layer of the interlayer dielectric layer 410 is left on the gate structures 401a, 401b. In other embodiments, when the interlayer dielectric layer 410 is completely removed and part of the second hard mask layer 412 on the substrate is exposed, the chemical mechanical polishing process will stop.

[0090] After that, the surface profile and thickness of the substrate were measured. Subsequently, one or more bulk cluster ion beam (GCIB) etchings can be used to remove dielectric films, such as the interlayer dielectric layer 410, the hard mask layer 411, and the hard mask on the structures (gate structures 403a and 403b). 模层412。 Mold layer 412. Some embodiments of the present invention perform primary cluster ion beam (GCIB) etching. This single-bulk cluster ion beam (GCIB) etching is used to remove the dielectric layers of different shapes above the dummy gate layer 435. The gas precursor of the gas cluster ion beam (GCIB) can be a mixed gas including some or all of the following gases: C x H y F z , NF 3 , HBr, SF 6 , Cl 2 , O 2 , N 2 , NH 3 , Or a dull gas (such as Ar or He). Some other embodiments of the present invention perform more than one bulk cluster ion beam (GCIB) etching, which uses different gas sources and/or different process conditions to remove different types of dielectric films. As described above, more than one profile and thickness measurement can be performed after bulk cluster ion beam (GCIB) etching to determine the target flatness and complete removal of the dielectric layer on the dummy gate layer 435.

[0091] Figure 4C Shows a cross-sectional view of the structure after cluster ion beam (GCIB) etching of some embodiments of the present invention. As mentioned above, multiple profile and thickness measurements and cluster ion beam (GCIB) etching can be performed to complete the planarization process. After the cluster ion beam (GCIB) etching is completed, a wet etching process can be performed to remove the damaged surface layer. Cluster ion beam (GCIB) etching is performed across the substrate with the help of profile and thickness data to achieve the target flatness without compromising the integrity of the gate structure. The process mechanism that uses a combination of chemical mechanical polishing, surface profile measurement and cluster ion beam (GCIB) etching to improve surface flatness is not only applicable to the PRG process, this mechanism can also be applied to the gate first process (no Dummy gate process). The front gate process can also benefit from improved flatness, and after the planarization process, micro-patterns can be patterned.

[0092] Another example of applying the above-mentioned planarization mechanism is to planarize the polysilicon layer above the diffusion region of the fin structure (silicon fin) of the FinFET technology. Figure 5A The device area 500 on the substrate 501 in some embodiments of the present invention is shown. The device region 500 has an oxide layer 502 and some silicon fins 503, 504, and 505. In some embodiments, the oxide layer 502 is used to fill the shallow trenches of the shallow trench isolation structure. The device area 500 also has a larger silicon structure 506. A polysilicon layer 510 is deposited on the oxide layer 502 and the silicon structures 503, 504, 505, and 506. The silicon structures 503, 504, 505, and 506 (fin structures) have a fin height "F". In order to form a fin field effect transistor (FINFET) structure, the polysilicon layer 510 needs to be planarized, leaving a thickness "H" (refer to curve 515), which is the height of the polysilicon gate located above the silicon structures 503, 504, 505, and 506, Such as Figure 5A Shown. Since there is no chemical mechanical polishing stop layer, it is difficult to polish the polysilicon layer 510 to a required flatness. In some embodiments, the flatness requirement is less than about +/-50 Angstroms.

[0093] In order to achieve the required flatness, before the polysilicon layer 510 reaches the final thickness (the thickness of H above the fin structure), the polysilicon layer 510 is removed and planarized using a chemical mechanical polishing process. Figure 5B The curve 525 shows the original polysilicon profile. Figure 5B The curve 520 of shows the substrate surface after chemical mechanical polishing in some embodiments of the present invention. Afterwards, the thickness of the polysilicon layer and the outline across the wafer and/or across the die on the substrate are measured. The profile and thickness data are used to flatten the substrate by cluster ion beam (GCIB) etching to the final thickness (curve 530) and meet the required flatness. As mentioned above, multiple profile and thickness measurements can be performed to complete the planarization process. After the cluster ion beam (GCIB) etching is completed, a wet etching process can be performed to remove the damaged surface layer. Cluster ion beam (GCIB) etching, with the help of profile and thickness data, allows etching across the substrate to achieve the target flatness.

[0094] The embodiment of the above mechanism improves the flatness of the substrate, and the flatness of the substrate is important for the improvement of patterning and device yield. The chemical mechanical polishing process is used to remove the film to planarize the substrate before reaching the final thickness or all the removed film is planarized. Next, measure the contour of the substrate and the thickness of the film. The gas cluster ion beam (GCIB) device will identify the location and how much thickness of the film needs to be removed based on the information provided. The gas cluster ion beam (GCIB) etches the final film layer to meet substrate uniformity and thickness goals. This mechanism improves flatness and meets the needs of advanced process technology.

[0095] An embodiment of the present invention provides a method of planarizing a substrate. The method includes depositing a first layer on a substrate with a device pattern on a surface. The contour of the element pattern gives the first layer deposited on the substrate a first surface contour. This method includes using chemical mechanical polishing to remove part of the first layer from the substrate to reduce the first surface profile. The method further includes collecting data on the second surface profile of the substrate after removing part of the first layer from the substrate using chemical mechanical polishing. In addition, this method includes performing gas cluster ion beam (GCIB) etching on the remaining part of the first layer above the element pattern, which uses the collected data of the second surface profile of the substrate to determine the different positions of the first layer How much to etch. Gas cluster ion beam (GCIB) etching reduces the second surface profile and improves the flatness of the substrate.

[0096] Another method of planarizing a substrate is provided in another embodiment of the present invention. The method includes depositing a first layer on a substrate with a gate structure on a surface, and after depositing the first dielectric layer, depositing a second dielectric layer on the substrate. The contour of the device pattern causes the first dielectric layer and the second dielectric layer deposited on the substrate to produce a first surface contour. The method further includes using chemical mechanical polishing to remove part of the second dielectric layer from the substrate to reduce the first surface profile. In addition, the method includes collecting data on the second surface profile of the substrate after removing part of the second dielectric layer from the substrate using chemical mechanical polishing. In addition, the method includes performing at least one gas cluster ion beam (GCIB) etching on the remaining part of the first dielectric layer and the second dielectric layer above the element pattern, which uses the collected second surface profile of the substrate The data determines how much the second dielectric layer and the first dielectric layer need to be etched at different positions. This at least one gas cluster ion beam (GCIB) etching reduces the second surface profile and improves the flatness of the substrate.

[0097] Although the present invention has disclosed the above preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make some changes and modifications without departing from the spirit and scope of the present invention. In addition, the present invention is not particularly limited to the process, apparatus, manufacturing method, composition, and steps of the embodiment described in the specific specification. Based on the disclosure of the specification of the present invention, those skilled in the art can further develop processes, devices, manufacturing methods, compositions and steps that have substantially the same functions or can substantially achieve the same results as those of the present invention. Therefore, the protection scope of the present invention should be defined by the appended claims.