Semiconductor structure and forming method thereof
A technology of semiconductors and conductive materials, used in semiconductor devices, semiconductor/solid-state device manufacturing, semiconductor/solid-state device components, etc., and can solve problems such as contact fragmentation and delamination
Active Publication Date: 2014-05-07
TAIWAN SEMICON MFG CO LTD
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Problems solved by technology
This causes additional stress in the joint area which can lead to joint cracking and / or other problems such as delamination
Method used
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[0018] The examples in the following description disclose how to form and use semiconductor structures. It must be understood, however, that these embodiments provide many possible inventive concepts and may be applied in many specific contexts. The specific embodiments are intended merely to illustrate specific ways to make and use the embodiments, and do not limit the scope of the inventions.
[0019] The advantage of the die edge contact technology is that it provides a more convenient test contact for 3D IC packaging and resists integrated circuit cracks caused by thermal stress. Moreover, the edge contacts can avoid damage to the integration of components caused by TSV (Through Substrate Via) penetrating the integrated circuit and possible metal pollution to the integrated circuit components.
[0020] figure 1 is a partial perspective view of die 101 in one embodiment of the present invention. Die 101 includes a substrate 102 having a protective layer 104 formed thereo...
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A semiconductor device utilizing die edge contacts is provided. An integrated circuit die has a post-passivation layer with a trench filled with a conductive material extending from a contact to a die edge, thereby forming a die edge contact. Optionally, a through substrate via may be positioned along the die edge such that the conductive material in the trench is electrically coupled to the through-substrate via, thereby forming a larger die edge contact. The integrated circuit die may be placed in a multi-die package wherein the multi-die package includes walls having a major surface perpendicular to a major surface of the integrated circuit die. The die edge contacts are electrically coupled to contacts on the walls of the multi-die package. The multi-die package may include edge contacts for connecting to another substrate, such as a printed circuit board, a packaging substrate, a high-density interconnect, or the like.
Description
technical field [0001] The present invention relates to a semiconductor component, and in particular to a semiconductor component with die edge contacts. Background technique [0002] Due to the continuous improvement in the integration density of various electronic components such as transistors, diodes, resistors, or capacitors, etc., the semiconductor integrated circuit industry has grown rapidly for some time. The main method to improve the above-mentioned integration density is to continuously reduce the structure size, so that more components can be integrated into a fixed area. [0003] The transformation of semiconductor packaging in the past few decades has impacted the entire semiconductor industry several times. The introduction of surface mount technology (SMT) and ball grid array (BGA) packaging is an important milestone for the high-throughput assembly of most IC components, reducing the pad spacing on printed circuit boards. In the structure of existing pack...
Claims
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IPC IPC(8): H01L23/485H01L23/31H01L21/768H01L21/78
CPCH01L2224/0557H01L25/0657H01L2225/06551H01L2224/05568H01L2924/0105H01L24/05H01L2924/01327H01L21/76898H01L2924/01047H01L2924/01078H01L2924/01006H01L23/481H01L2924/01073H01L2924/01079H01L2924/01074H01L2224/03825H01L2924/01005H01L2924/1434H01L2225/06565H01L2224/05147H01L2924/01013H01L24/03H01L2924/014H01L2225/06541H01L2224/05655H01L2224/0401H01L2924/01029H01L2224/05006H01L25/50H01L2224/03823H01L2924/01019H01L2224/05009H01L2924/01033H01L25/18H01L2924/01075H01L2924/00014H01L2924/351H01L2924/15787H01L2924/15788H01L2924/181H01L2924/12042H01L2924/14H01L2224/02371H01L2924/01046H01L2924/00H01L2224/05552
Inventor 赖怡仁周友华黄宏麟杨怀德
Owner TAIWAN SEMICON MFG CO LTD