Grid stack structure and manufacturing method thereof

Abstract

The invention relates to a grid stack structure and a manufacturing method of the grid stack structure; the grid stack structure is formed on a semiconductor substrate which also comprises symmetrical gap wall structures; the grid stack structure comprises a high K-grid dielectric layer and a first work function layer which are formed between the gap wall structures and sequentially positioned on the semiconductor substrate; the high K-grid dielectric layer is contacted with vertical side walls of the gap wall structures; a metal gate electrode is also formed on the first work function layer; and the top of the metal gate electrode is parallel and level to the tops of the gap wall structures. The problem that a gap appears in the metal gate electrode can be avoided by the grid stack structure, and the parasitic capacitance of a grid can be reduced.

Description

technical field [0001] The present invention relates to the field of semiconductor technology, and more specifically, the present invention relates to a gate stack structure and a manufacturing method thereof. Background technique [0002] With the continuous development of integrated circuit manufacturing technology, the feature size of MOS transistors is getting smaller and smaller. As the feature size of MOS transistors continues to shrink, in order to reduce the parasitic capacitance of the gate of MOS transistors and increase device speed, the gate stack structure of high-K gate dielectric layer and metal gate electrode is introduced into MOS transistors. [0003] In order to avoid the influence of the metal material of the metal gate electrode on other structures of the transistor, the gate stack structure of the metal gate electrode and the high-K gate dielectric layer is usually fabricated by a gate replacement (replacement gate) process. In this process, before the...

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Problems solved by technology

For example, in this process, since the gate length is small and the aspect ratio of the gate opening is high, it is difficult to deposit the gate electrode material into the gate opening, and voids (voids) in the metal gate electrode are likely to occur. ), thus affecting the performance of the gate electrode

In addition, in the gate stack structure formed by this process, the vertical sidewall of the gate opening is also covered with a high-K gate dielectric layer, which leads to an increase in the parasitic capacitance between the source-drain contact hole and the metal gate electrode

And the unnecessary increase of parasitic capacitance of the gate electrode will affect the switching speed of the device

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