Dynamic LDPC error correction code method for flash memory

A technology of LDPC code and memory, which is applied in the field of data error correction, can solve the problems of BCH code error correction ability restriction and reliability decline, and achieve the effect of improving error correction ability, reliability, and quantization accuracy

Active Publication Date: 2012-03-28
TSINGHUA UNIV
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Problems solved by technology

With the serious decline in the reliability of the new generation of 3b / cell NAND flash memory products, the limited redundant bits in the free storage area have severely restricted the error correction capability of the BCH code.

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  • Dynamic LDPC error correction code method for flash memory
  • Dynamic LDPC error correction code method for flash memory
  • Dynamic LDPC error correction code method for flash memory

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Embodiment Construction

[0026] In order to make the technical method and advantages of the present invention clearer, the present invention will be described in more detail below in conjunction with specific embodiments and with reference to the accompanying drawings.

[0027] LDPC code is a linear block code proposed by Gallager in his doctoral dissertation in 1962. Rediscovered by MacKay and Neal in 1996. LDPC code is considered to be the code with the best performance so far, and has been widely used in optical communication, mobile communication system and magnetic recording system. At present, the size of the manufacturing process of NAND flash memory is continuously reduced, and the most advanced manufacturing process of NAND flash memory has reached 19nm. In addition, multi-bit storage technology is also developing continuously. Can store 3-bit data information. However, these technologies make the device leakage of memory cells, the capacitive coupling effect between adjacent memory cells, ...

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Abstract

The invention discloses a dynamic LDPC error correction code method for a flash memory, which belongs to the field of datum error correction of the non-volatile memory. According to the method, the quantification precision of soft information of LDPC codes is changed according to the page error rate of the NAND type flash memory. The method of the invention has the following beneficial effects: 1, in the initial usage phase of the NAND type flash memory, the program erasing frequency of each page in the flash memory is small, so the page error rate is small when, and the LDPC code soft information with the quantification precision of 1-bit is adopted to improve the read access time of the NAND type flash memory and reduce the power consumption of an LDPC decoder; and 2, when the flash memory is continuously used, the page error rate gradually rises, and the quantification precision of the LDPC codes is increased, so the error correction capability of the LDPC codes is improved, and the reliability of the NAND type flash memory can be improved.

Description

technical field [0001] The invention belongs to the field of data error correction in non-volatile memory, in particular to a dynamic LDPC error correction code method applied in flash memory. Background technique [0002] NAND flash memory is widely used in portable electronic products such as MP3 players, smart phones, and tablet computers. An important trend in the development of NAND flash memory is the development of MLC (Multi-Level Cell) technology. MLC technology can store multi-bit information on a storage unit, so it can double the storage capacity and reduce the storage cost per bit. The current NAND flash memory in the market uses 2-bit storage in each storage unit (cell). MLC technology of bit information, that is, 2b / cell MLC technology. However, with the continuous improvement of the manufacturing process of NAND flash memory, the MLC technology for storing 3-bit information in each memory cell, that is, the 3b / cell MLC technology will be applied to a new ge...

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G11C29/42G11B20/18
Inventor 王雪强潘立阳周润德
Owner TSINGHUA UNIV
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