Low-power-consumption adaptive routing method in network on chip

Abstract

The invention relates to the technical field of networks on chip, and discloses a low-power-consumption adaptive routing method in a network on chip. The method comprises the following steps that: S1, distances between a source node and a destination node of a message in an x dimension direction and a y dimension direction are calculated respectively, if the sum of the distances is zero, routing is finished, otherwise, a step S2 is executed; S2, the network is divided into two virtual sub-networks x+y* and x-y*; and S3, the message enters into the virtual sub-network x+y* or x-y* for routing. In the method, the physical network is divided into two virtual sub-networks x+y* and x-y*, the interiors of the virtual sub-networks x+y* and x-y* both use a fully adaptive routing algorithm of the shortest path and a new EVC (Express Virtual Channel) flow control technology, data packets are injected into a corresponding virtual network according to the offset value of the destination node of the data packets relative to the source node, and the data packets are routed to the destination in a manner of adaptive routing. In the routing process of the data packets, an EVC is selected preferably, and an NVC (Normal Virtual Channel) is used when no idle EVC exists, so that the routing goes forward according to normal pipeline stages, the performance is improved and the power consumption is reduced.

Description

technical field [0001] The invention relates to the technical field of on-chip networks, in particular to a low-power adaptive routing method in on-chip networks. Background technique [0002] Due to the ever-increasing demand for communication bandwidth between multi-cores on a chip, the concept of Network on Chips (NoC) was proposed to specifically study and deal with communication problems between on-chip components such as multi-cores. In the field of network-on-chip, in addition to the bandwidth issue affecting performance, power consumption is also a key factor affecting the design of network-on-chip. Power consumption is mainly due to the movement of data in the network. Higher bandwidth will inevitably generate more power consumption. Therefore, how to balance the two conflicting factors of bandwidth and power consumption is crucial to the design of high-performance on-chip networks. important. Constructing a system-level power consumption model and proposing a low...

AI Technical Summary

Problems solved by technology

The ORION power consumption estimation model can only estimate the overall energy consumption of the on-chip network, and lacks a mechanism to measure the peak power consumption of the on-chip network during actual operation

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