Package of embedded chip and manufacturing method thereof

A technology of embedded chips and manufacturing methods, applied in the fields of semiconductor/solid-state device manufacturing, electrical components, semiconductor devices, etc., can solve problems such as process difficulties, increased process time, and increased costs

Active Publication Date: 2012-05-16
SILICONWARE PRECISION IND CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, the process of penetrating the encapsulant 13 is difficult, and the conductive material 100 needs to

Method used

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  • Package of embedded chip and manufacturing method thereof
  • Package of embedded chip and manufacturing method thereof
  • Package of embedded chip and manufacturing method thereof

Examples

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Example Embodiment

[0068] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification.

[0069] It should be noted that the structure, ratio, size, etc. shown in the drawings of this specification are only used to match the content disclosed in the specification for the understanding and reading of those skilled in the art, and are not used to limit the implementation of the present invention. Therefore, it does not have any technical significance. Any structural modification, proportional relationship change or size adjustment should still fall within the disclosure of the present invention without affecting the effects and objectives that the present invention can produce. The technical content can cover the range. At the same time, the terms such as "上" and "一" cited in this specification are only for ease of description...

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Abstract

The invention relates to a package of an embedded chip and a manufacturing method thereof. The package comprises: a dielectric layer, which has a first surface and a second surface that is opposite to the first surface; conductive projections, which are arranged in the dielectric layer and are exposed outside the dielectric layer; a chip, which is embedded in the dielectric layer; a line layer, which is arranged on the first surface of the dielectric layer; conductive blind holes, which are arranged in the dielectric layer and are electrically connected with the line layer, the chip and the conductive projection; and a first welding-resistant layer, which is arranged on the first surface of the dielectric layer and the line layer. Therefore, other electronic apparatuses can be externally connected by the conductive projections, so that a stacked structure is formed; and the technology is effectively simplified. In addition, the invention also provides a manufacturing method of a chip scale package.

Description

technical field [0001] The invention relates to a package and its manufacturing method, in particular to an embedded chip package and its manufacturing method. Background technique [0002] With the evolution of semiconductor technology, different packaging product types have been developed for semiconductor products. In order to pursue thinner, thinner and smaller semiconductor packages, a chip scale package (CSP) has been developed, which is characterized in that Chip-scale packages are only equal to or slightly larger than the chip size. [0003] U.S. Patent Nos. 5,892,179, 6,103,552, 6,287,893, 6,350,668 and 6,433,427 disclose a traditional CSP structure, which directly forms build-up layers on the chip without using chip carriers such as substrates or lead frames, and uses redistribution layer, RDL) technology to reconfigure the electrode pads on the chip to the desired position. [0004] However, the disadvantage of the above-mentioned CSP structure is that the appli...

Claims

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Application Information

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IPC IPC(8): H01L23/31H01L23/488H01L21/50H01L21/56
CPCH01L2224/73267H01L24/24H01L2224/04105H01L2224/32245H01L2224/92244H01L2924/181H01L2224/24H01L2224/24246H01L2924/00H01L2924/00012
Inventor 张江城廖信一邱世冠
Owner SILICONWARE PRECISION IND CO LTD
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