Package of embedded chip and manufacturing method thereof

Abstract

The invention relates to a package of an embedded chip and a manufacturing method thereof. The package comprises: a dielectric layer, which has a first surface and a second surface that is opposite to the first surface; conductive projections, which are arranged in the dielectric layer and are exposed outside the dielectric layer; a chip, which is embedded in the dielectric layer; a line layer, which is arranged on the first surface of the dielectric layer; conductive blind holes, which are arranged in the dielectric layer and are electrically connected with the line layer, the chip and the conductive projection; and a first welding-resistant layer, which is arranged on the first surface of the dielectric layer and the line layer. Therefore, other electronic apparatuses can be externally connected by the conductive projections, so that a stacked structure is formed; and the technology is effectively simplified. In addition, the invention also provides a manufacturing method of a chip scale package.

Description

technical field [0001] The invention relates to a package and its manufacturing method, in particular to an embedded chip package and its manufacturing method. Background technique [0002] With the evolution of semiconductor technology, different packaging product types have been developed for semiconductor products. In order to pursue thinner, thinner and smaller semiconductor packages, a chip scale package (CSP) has been developed, which is characterized in that Chip-scale packages are only equal to or slightly larger than the chip size. [0003] U.S. Patent Nos. 5,892,179, 6,103,552, 6,287,893, 6,350,668 and 6,433,427 disclose a traditional CSP structure, which directly forms build-up layers on the chip without using chip carriers such as substrates or lead frames, and uses redistribution layer, RDL) technology to reconfigure the electrode pads on the chip to the desired position. [0004] However, the disadvantage of the above-mentioned CSP structure is that the appli...

AI Technical Summary

Problems solved by technology

However, the process of penetrating the encapsulant 13 is difficult, and the conductive material 100 needs to be filled when forming the conductive via 10, so that the process time is increased and the cost is increased.

Images