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Glitch-free oversampling clock and data recovery

A technology of oversampling and data, applied in the direction of digital transmission system, electrical components, transmission system, etc., can solve the problems of inability to properly trigger the trigger, interference pulse, too small, etc.

Active Publication Date: 2012-05-16
TAIWAN SEMICON MFG CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However data jitter and phase errors between clock and data can cause glitches (pulses too small to properly trigger flip-flops or logic gates) in the recovered clock and data errors in the CDR
Furthermore, IC process variations, operating temperature and power supply variations also have a negative impact on the sampling window width and those on the recovered clock and data accuracy

Method used

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  • Glitch-free oversampling clock and data recovery
  • Glitch-free oversampling clock and data recovery
  • Glitch-free oversampling clock and data recovery

Examples

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Embodiment Construction

[0038] The making and using of preferred embodiments of the invention are discussed in detail below. It should be appreciated, however, that the present invention provides many applicable concepts that can be implemented in a wide variety of specific contexts. The specific embodiments discussed are merely illustrative of specific ways to make and use the invention, and do not limit the scope of the disclosure.

[0039] figure 1 For schematic purposes, an exemplary clock and data recovery (CDR) circuit is shown in accordance with some embodiments. The CDR circuit 100 includes an edge detector 102 , an edge selector 104 and a synchronization de-interference circuit 106 , and a phase selector 108 . When CDR circuit 100 receives serial input data, edge detection circuit 102 is caused to oversample multiple data samples during each data bit period using an oversampling circuit (not shown) and multiple clock phases at the reference clock input.

[0040] For example, the edge dete...

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Abstract

A clock and data recovery (CDR) circuit includes an edge detector, an edge selector, and a phase selector. The edge detector is arranged to detect edges of serial input data and to provide an edge detection result. The serial input data is oversampled utilizing multiple clock phases. The edge selector for selecting one of the multiple clock phases for a recovered clock is arranged to provide an edge selection result, to receive the last edge selection result as a first input, and to receive the edge detection result as a second input. The phase selector is arranged to provide the recovered clock and recovered data.

Description

technical field [0001] The present invention relates generally to an integrated circuit, and more particularly to a clock and data recovery circuit. Background technique [0002] In the field of high speed serial data communications, such as on the Universal Serial Bus, clock and data recovery (CDR) circuits are commonly used. In many applications, a high-speed data stream is sent without an accompanying clock signal. The CDR at the receiver generates a clock from an approximate frequency reference, which is then phase aligned to changes in the data stream. However data jitter and phase errors between clock and data can cause glitches (pulses too small to properly trigger flip-flops or logic gates) in the recovered clock and data errors in the CDR. Furthermore, integrated circuit process variations, operating temperature and power supply variations also have a negative impact on the sampling window width and those on the recovered clock and data accuracy. Contents of the...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H03K19/00
CPCH04L7/0338
Inventor 陈佑齐
Owner TAIWAN SEMICON MFG CO LTD