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Chip planarization process

A flattening process and chip technology, applied in the manufacture of electrical components, circuits, semiconductor/solid-state devices, etc., can solve problems such as damage to device performance and TIN structure damage on the front metal surface, to ensure integrity, reduce production costs, The effect of optimizing the process flow

Active Publication Date: 2013-12-25
FOUNDER MICROELECTRONICS INT
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

However, as the chamfering etching time increases, it will cause damage to the TIN structure on the metal surface of the front layer and damage the device performance, such as Figure 1e shown

Method used

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Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0037] to flatten image 3 The silicon wafer shown is an example.

[0038] After the front layer metal step 12 is formed on the silicon wafer 11, the first layer of filling oxide layer 13 is grown on the silicon wafer 11 by using PE CVD equipment, such as Figure 4 As shown, the material of the oxide layer 13 is silicon dioxide, and its thickness is 4500 angstroms.

[0039] Then perform chamfer etching to correct the surface angle of the oxide layer at the gap, and the etching amount is 2700 angstroms, such as Figure 5 shown.

[0040] Then use PE CVD equipment to grow the second layer of filling oxide layer, the thickness of the oxide layer is 900 angstroms, such as Figure 6 shown.

[0041] Perform chamfer etching again to correct the surface angle of the oxide layer at the gap, and the etching amount is 900 angstroms, such as Figure 7 shown.

[0042] Then use PE CVD equipment to grow the third layer of filling oxide layer, the thickness of the oxide layer is 14400 An...

Embodiment 2

[0045] The difference from Example 1 is that the thickness of the oxide layer filled for the first time is 5000 angstroms, and the etching amount of chamfer etching for the first time is 3000 angstroms; the thickness of the oxide layer filled for the second time is 1000 angstroms, and The etching amount of the second chamfer etching is 1000 angstroms; the thickness of the third filling oxide layer is 16000 angstroms, and the removal amount of the oxide layer by CMP operation is 10000 angstroms.

Embodiment 3

[0047]The difference from Example 1 is that the thickness of the oxide layer filled for the first time is 5500 angstroms, and the etching amount of chamfer etching for the first time is 3300 angstroms; the thickness of the oxide layer filled for the second time is 1100 angstroms, and The etching amount of the second chamfer etching is 1100 angstroms; the thickness of the third filling oxide layer is 17600 angstroms, and the removal amount of the oxide layer by CMP operation is 11000 angstroms.

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Abstract

The invention discloses a chip planarization process, comprising the following steps: developing a first filling oxidation layer with the thickness of 5000*(1+ / -10%) angstrom after a front layer metal step is formed on a silicon chip; subsequently carrying chamfering etching according to the etching amount of 3000* (1+ / -10%) angstrom to correct the surface angle of the oxidation layer at a gap; re-developing a second filling oxidation layer with the thickness of 1000*(1+ / -10%) angstrom; carrying out chamfering etching again according to the etching amount of 1000*(1+ / -10%) angstrom to correct the surface angle of the oxidation layer at a gap; re-developing a third filling oxidation layer with the thickness of 16000*(1+ / -10%) Angstrom; and finally carrying out CMP (Chip Multiprocessors) operation according to the oxidation layer removal amount of 10000* (1+ / -10%) angstrom. With the process of the invention, not only generation of voids at the gaps of the front layer metal step can be avoided, but also the integrity of the front layer metal structure can be guaranteed.

Description

technical field [0001] The invention belongs to the technical field of semiconductor device manufacturing technology, and in particular relates to a chip planarization process method, which is suitable for the occasion where the metal step gap of the front layer of the silicon chip is not less than 0.6 micron in the 0.5 micron chip manufacturing technology. Background technique [0002] In the early stage of chip planarization, when the step spacing of the front layer on the silicon wafer is very small, such as 0.6 microns, the surface angle will be very sharp after the oxide layer is filled with plasma-enhanced chemical vapor deposition (PE CVD) equipment, such as Figure 1a shown. As the thickness of the filled oxide layer increases, voids will be formed in the gaps of the front steps, such as Figure 1b shown. As a result, structural defects of the device are caused, the reliability of the device is reduced, and the yield rate of the product is affected. [0003] Plasma...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/02H01L21/316H01L21/311H01L21/302
Inventor 陈建国席华萍贺冠中周华强
Owner FOUNDER MICROELECTRONICS INT
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