Phase-locked loop

Abstract

The invention provides a phase-locked loop. The phase-locked loop comprises an active filter, a voltage-controlled oscillator, two phase detectors, a charge pump and a digital/analogue converter, wherein the voltage-controlled oscillator generates an oscillation signal according to a control signal provided by the output end of the active filter; a first phase detector generates a phase difference signal according to a reference signal and a feedback signal corresponding to the oscillation signal; the charge pump provides a charging current to a first input end of the active filter according to the phase difference signal; a second phase detector generates a digital reference voltage according to the phase difference of the reference signal and the feedback signal; and the digital/analogue converter converts the digital reference voltage into an analogue reference voltage, and provides the analogue reference voltage to a second input end of the active filter.

Description

technical field [0001] The present invention relates to phase-locked loops, and in particular to the circuit architecture of phase-locked loops. Background technique [0002] In today's computer systems and communication systems, a phase-locked loop that can provide an oscillating signal with an accurate frequency plays an indispensable and important role. Taking the wireless communication system as an example, the transmitting end usually uses the oscillating signal generated by the phase-locked loop as the reference for sending the signal. The quality of the signal. [0003] figure 1 Shown is the structure diagram of the first type (type-I) phase-locked loop. The loop 10 includes a phase detector 11 , a charge pump 12 , a filter 13 composed of a resistor R and a capacitor C, a voltage-controlled oscillator 14 and a frequency divider 15 . Since the resistor R forms a leakage path between the input terminal of the voltage-controlled oscillator 14 and the ground terminal,...

AI Technical Summary

Problems solved by technology

Although this structure does not have the problem of high surge energy of the first type phase-locked loop, the speed of charging / discharging the capacitor C1 by the second charge pump 22B will directly limit the locking speed of the loop 20

In addition, this damping phenomenon also results in a longer lock-up time required for the circuit 20

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