Verifying multi-cycle self refresh operation of semiconductor memory device and testing the same

Abstract

A semiconductor memory device includes a memory cell array, a tag information register, a refresh control circuit and a DQ pin. The memory cell array includes multiple memory cells divided into first cells and second cells according to corresponding data retention times. The tag information register stores refresh cycle information for each wordline connected to the first cells and the second cells. The refresh control circuit is configured to generate a refresh enable signal and a refresh address based on the refresh cycle information. The DQ pin is configured to output the refresh enable signal, the refresh address and data stored in the memory cell array.

Description

[0001] Cross references to related applications [0002] According to 35U.S.C.§119, priority is required for Korean Patent Application No. 10-2010-0120719 filed at the Korean Intellectual Property Office on November 30, 2010, the entire contents of which are incorporated herein by reference. Background technique [0003] The illustrative embodiment relates to a semiconductor device, and more specifically, to a semiconductor memory device and a method of verifying multi-cycle self-refresh, and a test system using the method. [0004] Generally, a DRAM cell stores data in a capacitor as a charge configuration, and the charge (data) is lost due to leakage current. Therefore, the lost data needs to be stored in the DRAM cell again to prevent permanent data loss, which is called a refresh operation. [0005] However, DRAM cells can have different data retention characteristics. That is, some DRAM cells may have a shorter data retention time than other DRAM cells. Therefore, the refresh o...

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Problems solved by technology

Therefore, the refresh operation must be performed based on the DRAM cell with the shortest data retention time, which requires more power consumption

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