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High-speed low-power WTA (winner-take-all) sensitive amplifier

A sensitive amplifier and low power consumption technology, which is applied in the field of high-speed and low-power WTA sensitive amplifiers, can solve the problems of large power consumption and slow amplification speed, and achieve the effect of increasing the amplification speed and reducing power consumption

Inactive Publication Date: 2014-04-23
PEKING UNIV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0010] Although the traditional WTA sense amplifier solves the restriction problem of the bit line capacitance on the speed of the sense amplifier, the traditional WTA sense amplifier itself has the defects of large power consumption and slow amplification speed, but the existing technology has not been able to solve the problem make improvements

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  • High-speed low-power WTA (winner-take-all) sensitive amplifier
  • High-speed low-power WTA (winner-take-all) sensitive amplifier

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Embodiment Construction

[0022] The specific implementation manners of the present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments. The following examples are used to illustrate the present invention, but are not intended to limit the scope of the present invention.

[0023] figure 2 It is a schematic structural diagram of a high-speed low-power WTA sense amplifier according to an embodiment of the present invention; refer to figure 2, the amplifier in this embodiment includes: a sequentially connected current transmission circuit, an amplification trigger circuit, and an amplification circuit, wherein the amplification trigger circuit includes: a first NMOS transistor (ie, "N1" in the figure), a second NMOS transistor (that is, "N2" in the figure), the third NMOS transistor (that is, "N3" in the figure), the fourth NMOS transistor (that is, "N4" in the figure), the fifth NMOS transistor (that is, "N5" in the figure) ), and the sixt...

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Abstract

The invention which discloses a high-speed low-power WTA sensitive amplifier relates to the technical field of integrated circuits. The high-speed low-power WTA sensitive amplifier comprises, sequentially connected, a current transmission circuit, an amplification trigger circuit and an amplification circuit, and the amplification trigger circuit comprises a first NMOS (negative metal-oxide semiconductor) tube, a second NMOS tube, a third NMOS tube, a fourth NMOS tube, a fifth NMOS tube and a sixth NMOS tube. According to the invention, two pseudo current sources are arranged, so the power consumption of the WTA sensitive amplifier is reduced, and the amplification speed is improved.

Description

technical field [0001] The invention relates to the technical field of integrated circuits, in particular to a WTA sensitive amplifier with high speed and low power consumption. Background technique [0002] The sense amplifier is an important part of the static random access memory (SRAM) peripheral circuit, and its performance greatly affects the performance of the entire SRAM. As the level of integration increases, increased bit line load capacitance becomes a major obstacle limiting the performance of sense amplifiers. [0003] Traditional voltage-type sense amplifiers require between OUT and terminal to establish a differential voltage often requires bit lines BL and The same differential voltage is established at the terminals, and the increased load capacitance of the bit line will increase the time to establish the differential voltage of the bit line, which will degrade the performance. Since, under the trend of gradually shrinking size, the capacitance of the ...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G11C7/06
Inventor 贾嵩张洵王源
Owner PEKING UNIV