Memory and manufacturing method thereof
A manufacturing method and memory technology, which is applied in the field of memory and memory manufacturing, and can solve the problems of reduced distance between doped regions and punch-through voltage, etc.
Active Publication Date: 2012-07-11
SEMICON MFG INT (SHANGHAI) CORP +1
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- Application Information
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Problems solved by technology
However, reducing the size of the gate 16 changes the effective size of the storage device, increasing the dose and energy of ion implantation will increase the size of the doped region in the horizontal plane, reducing the distance between the doped regions, and easily causing punch-through voltage (punch through) generation
Method used
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[0029] In order to make the above objects, features and advantages of the present invention more comprehensible, specific implementations of the present invention will be described in detail below in conjunction with the accompanying drawings.
[0030] In the following description, many specific details are set forth in order to fully understand the present invention, but the present invention can also be implemented in other ways than those described here, so the present invention is not limited by the specific embodiments disclosed below.
[0031] In order to solve the problems described in the background art, the inventors of the present invention provide a method of manufacturing a memory. refer to image 3 , shows a schematic flow chart of an embodiment of the memory manufacturing method of the present invention. This embodiment takes NROM memory as an example, and the memory manufacturing method includes the following steps:
[0032] Step S1, providing a substrate on wh...
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Abstract
The invention provides a memory and a manufacturing method thereof. The manufacturing method comprises the following steps of: providing a substrate, wherein grid structures are formed on the substrate, and a substrate epitaxial layer is formed on the substrate at the both sides of the grid structures; doping the substrate epitaxial layer and the substrate arranged below the substrate epitaxial layer, so as to form a bit line; and forming an insulating layer on the bit line and forming word lines on the insulating layer and the grid structures. The memory comprises the substrate, the grid structures arranged on the substrate in sequence, the substrate epitaxial layer arranged on the substrate at the both sides of the grid structure, doping areas formed on the substrate epitaxial layer and the substrate, the insulating layer arranged on the substrate epitaxial layer, and the word lines covering the insulating layer and the grid structures. According to the inveniton, the resistance of the bit line is reduced.
Description
technical field [0001] The invention relates to the field of semiconductor manufacturing, in particular to a method for manufacturing a memory and a memory. Background technique [0002] With the continuous development of modern high-tech industries represented by electronic communication technology, the total output value of the world's integrated circuit industry is growing at a rate of 30% every year. The memory is an important part in the integrated circuit, its size is small, the density is high, and it is widely used in the semiconductor field. [0003] Nitride Programmable Read-Only Memory (NROM) is a memory with high storage capacity. refer to figure 1 , shows a top view of a NROM in the prior art. The NORM includes word lines WL arranged in rows and bit lines BL arranged in columns. In order to simplify the drawings, only four bit lines 11, 12, 13, 14 and four word lines are shown in the drawings. 21, 22, 23, 24. The word line WL is used to gate the memory cell...
Claims
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Login to View More IPC IPC(8): H01L21/8247H01L21/28H01L27/115H01L29/423
Inventor 徐伟中陈福刚
Owner SEMICON MFG INT (SHANGHAI) CORP