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On-chip debugging circuit based on long and short scan chains and JTAG (joint test action group) interface

An on-chip debugging and scan chain technology, applied in electrical digital data processing, instruments, computing, etc., can solve the problems of slow debugging transmission rate and low communication efficiency, and achieve the effects of shortening the development cycle, low interference, and high debugging efficiency

Inactive Publication Date: 2012-07-18
SHANGHAI UNIV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Solve the problems of slow debugging transmission rate and low communication efficiency, and the modular debugging circuit is easy to reuse IP

Method used

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  • On-chip debugging circuit based on long and short scan chains and JTAG (joint test action group) interface
  • On-chip debugging circuit based on long and short scan chains and JTAG (joint test action group) interface
  • On-chip debugging circuit based on long and short scan chains and JTAG (joint test action group) interface

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0028] see figure 1 , this is an on-chip debugging circuit based on long and short scan chains and a JTAG interface, characterized in that the debugging interface module (1) includes a debugging interface module (1), a debugging exception control module (2), a debugging temporary storage module (3) and The long and short scan chain modules (4) are characterized in that the debugging host (5) is connected to the debugging interface module (1), and the other end of the debugging interface module (1) is connected to the long and short scan chain modules (4), and the long and short scan chain modules (4) are respectively Connect the microprocessor core (6) and the debugging exception control module (2), the debugging exception control module (2) receives the data sent by the long and short scan chain module (4), sets data breakpoints and instruction breakpoints, and triggers debugging exceptions , and then send the interrupt signal to the microprocessor for debugging; the debuggin...

Embodiment 2

[0030] This embodiment is basically the same as Embodiment 1, and the special features are as follows:

[0031] The debugging interface module (1) is a channel for data exchange between the microprocessor core (6) and the debugging host (5). Such as figure 2As shown, the debug interface module (1) includes instruction register (7), instruction decoder (8), data register group (9), TAP controller (10), multiplexer 1 (11) and multiplexer Device 2 (12), the debugging interface module (1) is connected to the debugging host (5) through five wires TDI, TDO, TMS, TRST, TCK, and the other end of the debugging interface module (1) is connected to the long and short scan chain module (4) connected; the data register group (9) includes a bypass register (1'), a microprocessor number register (2'), a scan chain selection register (3'), a long scan chain register (4') and a short scan Chain registers (5'), these data registers are connected to the TDI line, and the other end is conn...

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Abstract

The invention relates to an on-chip debugging circuit based on long and short scan chains and JTAG (joint test action group) interface. The invention aims at providing the core of the microprocessor with powerful and flexible debugging functions. The on-chip debugging circuit includes a debugging interface module, a debugging exception control module, a debugging temporary storage module and long and short scan chain modules. The on -chip debugging circuit transmits debugging commands and data issued by a debugging host through the JTAG interface to the debugging interface module, the commands are decoded by a test access controller, the long and short scan chain modules transmit the decoded commands to the core of the microprocessor and the debugging exception control module, and the debugging exception control module completes the debugging exception function setting. The debugging functions include setting breakpoints for the program for single-step control, reading and modifying general registers of the microprocessor core, controlling program operation on the processor, and processing all types of exceptions. The debugging temporary storage module saves the running state of the microprocessor core when debugging functions are triggered, and when the microprocessor core exits debugging functions, restores the original operating state.

Description

technical field [0001] The invention relates to an on-chip debugging circuit based on an interface between long and short scan chains and a JTAG (Joint Test Action Group), and specifically relates to the field of microprocessor core debugging technology. Background technique [0002] With the rapid development of integrated circuit manufacturing technology, the development of microprocessor core is also changing with each passing day. The general development trend of the microprocessor core in the world today is that the function is more and more powerful, and the working frequency is higher and higher. Especially in the 21st century, the era of implementing a more complex system on a silicon chip has come. This is System on Chip (SoC), and the embedded microprocessor core is the core of the system chip. Embedded systems are being widely used in various fields at an unprecedented speed, such as: industrial control, information appliances, automotive electronics, wireless c...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F11/267
Inventor 毕卓匡旭晖徐美华
Owner SHANGHAI UNIV