On-chip debugging circuit based on long and short scan chains and JTAG (joint test action group) interface
An on-chip debugging and scan chain technology, applied in electrical digital data processing, instruments, computing, etc., can solve the problems of slow debugging transmission rate and low communication efficiency, and achieve the effects of shortening the development cycle, low interference, and high debugging efficiency
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Embodiment 1
[0028] see figure 1 , this is an on-chip debugging circuit based on long and short scan chains and a JTAG interface, characterized in that the debugging interface module (1) includes a debugging interface module (1), a debugging exception control module (2), a debugging temporary storage module (3) and The long and short scan chain modules (4) are characterized in that the debugging host (5) is connected to the debugging interface module (1), and the other end of the debugging interface module (1) is connected to the long and short scan chain modules (4), and the long and short scan chain modules (4) are respectively Connect the microprocessor core (6) and the debugging exception control module (2), the debugging exception control module (2) receives the data sent by the long and short scan chain module (4), sets data breakpoints and instruction breakpoints, and triggers debugging exceptions , and then send the interrupt signal to the microprocessor for debugging; the debuggin...
Embodiment 2
[0030] This embodiment is basically the same as Embodiment 1, and the special features are as follows:
[0031] The debugging interface module (1) is a channel for data exchange between the microprocessor core (6) and the debugging host (5). Such as figure 2As shown, the debug interface module (1) includes instruction register (7), instruction decoder (8), data register group (9), TAP controller (10), multiplexer 1 (11) and multiplexer Device 2 (12), the debugging interface module (1) is connected to the debugging host (5) through five wires TDI, TDO, TMS, TRST, TCK, and the other end of the debugging interface module (1) is connected to the long and short scan chain module (4) connected; the data register group (9) includes a bypass register (1'), a microprocessor number register (2'), a scan chain selection register (3'), a long scan chain register (4') and a short scan Chain registers (5'), these data registers are connected to the TDI line, and the other end is conn...
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