Restoration device and restoration method for storage chip

Abstract

The invention provides a restoration device and a restoration method for a storage chip. The restoration device is positioned inside the storage chip, and comprises a data comparison module, a misaddress register and a saving module, wherein the data comparison module is used for comparing data in a current address of the storage chip with preset target data when the storage chip is read in parallel by using automatic testing equipment; the misaddress register is used for recording the current address as a misaddress when data in the current address is different from the preset target data; and the saving module is used for saving the misaddress in the misaddress register after the storage chip is read. According to the device and the method, parallel restoration of the storage chip can be realized, and the restoration speed and success rate of the storage chip can be increased.

Description

technical field [0001] The invention relates to the technical field of semiconductor chips, in particular to a repairing device and method for a memory chip. Background technique [0002] With the rapid development of microelectronics technology, parallel chip testing has been introduced into integrated circuit fields such as printed circuit boards, communication products and system-on-chips, and has been widely used. Parallel chip testing refers to completing multiple test tasks at the same time, including completing the testing of multiple chips under test at the same time, or running multiple test tasks asynchronously or synchronously on a single chip under test, and completing the test tasks at the same time Measurement of multiple parameters of the chip. [0003] The basic storage unit of a memory chip is a memory cell. In order to ensure the safety and reliability of the data in the memory chip, it usually does not allow a memory cell to be damaged. Therefore, in the ...

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Problems solved by technology

[0005] It can be seen that in order to record the error addresses of different memory chips, the existing memory chip repair method needs to read each memory chip serially; The serial repair of each memory chip is performed at the wrong address, which violates the original intention of parallel testing, resulting in a reduction in the repair speed of memory chips

[0006] In addition, due to the hardware limitation of ATE, it can only provide registers with limited space; like this, when there are a large number of (such as 1024) error addresses in each memory chip, 32 (32 is the number of parallel measurements) memory chips will be 32×1024 error addresses are generated, and it is difficult for ATE to record the error addresses of all memory chips, resulting in the failure of memory chip repair

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