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Method for measuring junction temperature and thermal resistance of metal-oxide semiconductor tube

A semiconductor tube and measurement method technology, applied in the direction of single semiconductor device testing, material thermal development, etc., can solve problems such as multi-time, high cost, and complicated operation methods, and achieve the effect of simple operation, low cost, and wide application range

Active Publication Date: 2014-12-10
SOUTHEAST UNIV
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  • Abstract
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  • Claims
  • Application Information

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Problems solved by technology

However, the structure of the infrared scanning equipment is complicated, the operation method is complicated, and the test efficiency is low. It takes more time; the cost is high; The assessment of finished devices or chips cannot meet the requirements

Method used

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  • Method for measuring junction temperature and thermal resistance of metal-oxide semiconductor tube
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  • Method for measuring junction temperature and thermal resistance of metal-oxide semiconductor tube

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Embodiment Construction

[0032] A method for measuring the junction temperature and thermal resistance of metal oxide semiconductor tubes,

[0033] Step 1 Place the insulating substrate with the device under test in the temperature control box, and adjust the temperature control box to 25°C. According to the range of the safe working area of ​​the device under test, and ensure that the device under test can work normally, give A DC voltage is applied across the drain-source of the device under test,

[0034] Step 2: Apply a grid DC operating voltage on the grid, and measure the current at both ends of the drain and source of the device under test when the voltage on the grid is a DC operating voltage,

[0035] Step 3 remove the DC operating voltage on the grid, and then apply a square wave pulse voltage on the grid, the amplitude of the square wave pulse voltage is equal to the DC operating voltage described in step 2, the duty cycle is less than 1% and the period is not Greater than 1 millisecond, i...

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Abstract

The invention discloses a method for measuring the junction temperature and thermal resistance of a metal-oxide semiconductor tube. The method comprises the following steps of: placing an insulating substrate with a device to be measured into a temperature control box, and adjusting the temperature control box to 25 DEGC; applying a DC (direct current) voltage to the drain end and source end of the device to be measured, and applying a grid DC working voltage to the grid; measuring the current at the drain and source ends of the device to be measured when the voltage on the grid is a DC working voltage; removing the DC working voltage on the grid; applying a square-wave pulse voltage to the grid; gradually increasing the temperature in the temperature control box, wherein the maximum temperature does not exceed the junction temperature of the measured device; continuously measuring the leakage current at the drain and source ends of the device to be measured; and when the measured leakage current at the drain and source ends of the device to be measured is equal to the current at the drain and source ends of the device to be measured, calculating the thermal resistance of the device to be measured by taking the temperature in the temperature control box as an equivalent junction temperature.

Description

technical field [0001] The technology belongs to the technical field of semiconductor device measurement in microelectronic technology, and in particular relates to a method for measuring junction temperature and thermal resistance of a metal oxide semiconductor tube. Background technique [0002] After the chip manufacturing of large-scale integrated circuits is completed, except for the case of secondary integration using thick film process or thin film process, packaging is required in most cases. The packaging of large-scale integrated circuits is also called the post-process. The function of packaging is to provide electrical connection and mechanical load for the chip, making it easy to operate and use, providing a standardized installation structure and size for users of large-scale integrated circuits, and preventing the chip from being subjected to external forces, scratches, water vapor or other Corrosion of harmful gases, sometimes multiple chips can be packaged ...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G01R31/26G01N25/20
Inventor 钱钦松刘斯扬张頔孙伟锋陆生礼时龙兴
Owner SOUTHEAST UNIV
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