3D encapsulation method

Abstract

The invention provides a three-dimensional encapsulation method which comprises the following steps of: providing a semiconductor substrate and a support substrate, wherein the semiconductor substrate sequentially comprises a heavy doping layer and a light doping layer on the surface of the heavy doping layer, and the light doping layer comprises at least one semiconductor device; forming an insulating layer on the surface of the semiconductor substrate and / or support substrate; by taking the insulating layer as an intermediate layer, attaching the semiconductor substrate and the support substrate together; removing the heavy doping layer in the semiconductor substrate to expose the light doping layer by a self-stop corrosion technology; forming multiple through holes in the light doping layer, wherein the positions of the through holes correspond to the positions of the pads of the semiconductor device; exposing the pads of the semiconductor device; and filling the through holes by conductive fillers. The method provided by the invention has the advantages that: by adopting the semiconductor substrate with the light doping layer and the heavy doping layer, the thickness of the thinned substrate can be reduced while guaranteeing the flatness of the substrate surface.

Description

technical field [0001] The invention relates to the field of semiconductor packaging, in particular to a three-dimensional packaging method. Background technique [0002] Future electronic systems will need to meet the increasing requirements for small size, light weight, high-frequency and high-speed operation, low power consumption, sensitivity, multi-function and low cost. Three-dimensional packaging is an attractive way to meet the requirements of these aspects, and it has the advantages of reducing the volume and increasing the utilization rate of substrate materials. [0003] Advanced three-dimensional packaging technology requires the thickness of the chip to be continuously reduced. Thinning the back of the semiconductor substrate of the manufactured device is an extremely important process in the packaging manufacturing process. Ultra-precision grinding, grinding, polishing, and corrosion reduce the thickness of the semiconductor substrate on the back. Widely used ...

AI Technical Summary

Problems solved by technology

[0004] However, in the current three-dimensional packaging process, it is difficult for the existing thinning technology to meet the flatness requirements of lithography while thinning the thinned substrate to 50 μm.

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