Signed multiply-accumulate algorithm method using adder tree structure

An adder tree and multiply-accumulate technology, which is applied to instruments, calculations, and electrical digital data processing, etc., can solve problems such as recalculation, and achieve the effect of small area and convenient expansion

Inactive Publication Date: 2012-09-19
深圳市清友能源技术有限公司
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Problems solved by technology

However, because the DA distribution algorithm needs to calculate the data in advance, a large amount of CPU memory is required to store the data. For a 1024-order FIR filter with a 16-bit word width, the required memory size is 2^1024*2 bytes. It is difficult for many embe

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  • Signed multiply-accumulate algorithm method using adder tree structure
  • Signed multiply-accumulate algorithm method using adder tree structure
  • Signed multiply-accumulate algorithm method using adder tree structure

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Embodiment

[0017] When considering the following multiply-accumulate calculation:

[0018] Get N=6, c and x all are the complement code operand of word length 8+1 sign bit. When multiplying the accumulator, the operand D[x] is first sent to the shift register Rx, and the operand c[n] and its {-c[n] 补} is sent to another register. Driven by the synchronous clock, all operands x are shifted to the right at the same time, and the data selection switches M1-M6 select the 6 operands input to the adder tree A1 according to the lowest bit of the R1-R6 shift register. c is still 0, for example: under a certain clock drive, the lowest bits of the six shift registers R1-R6 are [1, 1, 0, 1, 0, 1] respectively, then the six input terminals of the adder tree A1 The operands are {c[1], c[2], 0, c[4], 0, c[6]}. The adder tree A1 outputs the sum of the six operands, which is sent to the accumulator M1 and added to the previously shifted and accumulated value, and stored as a new value. After the ne...

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Abstract

The invention relates to a hardware multiply-accumulate algorithm and particularly relates to a signed multiply-accumulate algorithm method using an adder tree structure. According to the method, data are divided into two parts, i.e. coefficient items and data items, by adopting a complement form, the data items are decomposed into bit units according to a binary principle, the coefficient items are subjected to binary multiplication with bits of the data items according to an addition allocation principle, and the products are subjected to binary accumulation so as to obtain a final output result. The signed multiply-accumulate algorithm method using the adder tree structure overcomes the disadvantage of fixed coefficients of the original DA distributed algorithm and does not need a large number of ROMs (Read Only Memories) to serve as a coefficient table, the occupied area of a chip is smaller, the multiply-accumulate calculation of signed numbers is realized, and the extension is convenient, so that the signed multiply-accumulate algorithm method is especially suitable for the realization of a programmable logic device.

Description

Technical field: [0001] The invention relates to a hardware multiply-accumulate algorithm, in particular to a method for a signed multiply-accumulate algorithm using an adder tree structure. Background technique: [0002] At present, the multiply-accumulate algorithms commonly used in the field of digital signal processing are mainly traditional multiplier and accumulator algorithms and DA distributed algorithms. Among them, the steps of the multiplier and accumulator algorithm running in the CPU are as follows, the multiplication is calculated first and then the addition is calculated, and the above-mentioned process is repeated according to the number of coefficient items calculated as required. The disadvantage of this algorithm is that it takes a lot of time for the CPU to do a multiplication operation, and when there are many coefficients, especially when doing high-order FIR filter calculations, it is necessary to repeat thousands of multiplication operations for each ...

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Application Information

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IPC IPC(8): G06F7/544
Inventor 柳海龙
Owner 深圳市清友能源技术有限公司
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