Shift register unit and gate drive device

Abstract

The invention provides a shift register unit and a gate drive device. The shift register unit comprises a latch and a control circuit, wherein the control circuit comprises a first thin film transistor, a second thin film transistor and a third thin film transistor; the gate of the first thin film transistor is connected with a clock signal input end; the source of the first thin film transistor is connected with a signal input end; the drain of the first thin film transistor is connected with the input end of the latch; the gate of the second thin film transistor is connected with the clock signal input end; the source of the second thin film transistor is connected with a first signal output end; the gate of the third thin film transistor is connected with the signal input end; the source of the third thin film transistor is connected with a high-level signal input end; the drain of the third thin film transistor is connected with the drain of the second thin film transistor; the latch comprises a first phase inverter and a second phase inverter which are connected with each other end to end; the input end of the latch is connected with a second signal output end; the output end of the latch is connected with the first signal output end; and the levels of output signals of the first signal output end and the second signal output end are opposite. According to the shift register unit, the circuit is simple in structure, a small number of signal wires are arranged, the power consumption is low, and the area of a layout is small.

Description

technical field [0001] The present invention relates to the field of display technology, in particular to a shift register unit and a gate driving device. Background technique [0002] The gate driving device of the display is used to provide driving signals for the gate lines, and the gate driving device includes multiple cascaded shift register units, such as figure 1 Shown is a schematic structural diagram of a shift register unit in the prior art, the shift register unit includes: 2 latches 101 and 4 transmission gates 102, wherein one latch 101 is used for programming, and the other latch The register 101 is used to latch the output signal, and the transfer gate 102 is used to control the latch 101 to program or latch the output signal. From figure 1 It can be seen from the figure that each latch 101 is composed of two inverters (the Reset signal input to the Reset (reset) signal input terminal of the NAND gate in the figure is high level, so the NAND gate is also equ...

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Problems solved by technology

[0003] from figure 1 It can be seen from the figure that the existing shift register unit needs two latc

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