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Non-volatile memory compatible with CMOS (complementary metal oxide semiconductor) logic process and preparation method of non-volatile memory

A non-volatile, memory technology, used in semiconductor/solid-state device manufacturing, electrical solid-state devices, semiconductor devices, etc., can solve the problems of easy loss of written data, affect reliability, complexity, etc., to improve data storage time, The effect of improving the reliability of use and reducing the cost of use

Active Publication Date: 2015-06-17
浙江锋华创芯微电子有限公司
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

The combination of non-volatile memory (NVM) technology and traditional logic technology will make the process a more complex and expensive combination; since the typical usage of NVM for SoC applications is in relation to the overall The chip size is small, so this practice is not advisable
At the same time, due to the working principle of the existing non-volatile memory, the written data is easily lost, which affects the reliability of use

Method used

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  • Non-volatile memory compatible with CMOS (complementary metal oxide semiconductor) logic process and preparation method of non-volatile memory
  • Non-volatile memory compatible with CMOS (complementary metal oxide semiconductor) logic process and preparation method of non-volatile memory
  • Non-volatile memory compatible with CMOS (complementary metal oxide semiconductor) logic process and preparation method of non-volatile memory

Examples

Experimental program
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Effect test

Embodiment 1

[0069] like figure 1 and Figure 13 Shown: In order to make the non-volatile memory compatible with the CMOS logic process and enable the non-volatile memory to store for a longer period of time, the non-volatile memory includes a P conductivity type substrate 1, a P conductivity type substrate 1 The material is silicon. At least one memory cell 100 is provided on the upper part of the P conductivity type substrate 1, and the memory cell 100 includes a PMOS access transistor 110, a control capacitor 120 and a programming capacitor 130, and a gate electrode is deposited on the surface of the P conductivity type substrate 1. The dielectric layer 15 , the gate dielectric layer 15 covers the surface corresponding to the memory cell 100 , and the PMOS access transistor 110 , the control capacitor 120 and the programming capacitor 130 are isolated from each other by the domain dielectric region 14 in the P conductivity type substrate 1 . The domain dielectric region 14 is located ...

Embodiment 2

[0098] like figure 2 and Figure 25 Shown: In this embodiment, the semiconductor substrate is an N-conductive type substrate 39. When the N-conductive type substrate 39 is used, there is no need to form the second N-type region 3 in the N-conductive type substrate 39, that is, the second P-type region 5 and the second P-type region 5. The three P-type regions 31 are in direct contact with the N-type conductivity type substrate 39 , and at the same time, the first N-type region 2 and the third N-type region 4 are also in direct contact with the N-type conductivity type substrate 39 . After adopting the N conductive type substrate 39 , the rest of the structure is the same as that of Embodiment 1.

[0099] like Figure 15~Figure 25 Shown: the non-volatile memory of the above structure can be realized through the following process steps, specifically:

[0100] a. An N conductive type substrate 39 is provided, and the N conductive type substrate 39 includes a first main surfac...

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Abstract

The invention relates to a non-volatile memory compatible with a CMOS (complementary metal oxide semiconductor) logic process and the preparation method of the non-volatile memory. The non-volatile memory comprises a semiconductor substrate, wherein a plurality of memory cells for storage are arranged on the upper part inside the semiconductor substrate; a plurality of isolation grooves are arranged at the upper part inside the semiconductor substrate; an isolation medium is arranged inside each isolation groove to form a field medium area; a transistor inside each memory cell is mutually isolated from a capacitor through the field medium area; a gate medium layer is deposited on the first main surface of the semiconductor substrate; the gate medium layer covers a notch of each isolation groove and covers the first main surface of the semiconductor substrate; a P+ floating gate electrode is arranged above the top angle of each isolation groove, and the P+ floating gate electrode is arranged on the gate medium layer and distributed correspondingly to the top angle of each isolation groove. The non-volatile memory disclosed by the invention can be compatible with the CMOS logic process; the data retention time is improved; and the use reliability of the non-volatile memory is improved.

Description

technical field [0001] The invention relates to a non-volatile memory and a preparation method thereof, in particular to a non-volatile memory compatible with a CMOS logic process and a preparation method thereof, in particular to a non-volatile memory capable of improving data retention time A memory and a preparation method thereof belong to the technical field of integrated circuits. Background technique [0002] For system-on-chip (SoC) applications, it is the integration of many functional blocks into an integrated circuit. The most common SoCs include a microprocessor or microcontroller, static random access memory (SRAM) modules, non-volatile memory, and logic blocks for various special functions. However, conventional non-volatile memory processes, which typically use stacked-gate or split-gate memory cells, are not compatible with conventional logic processes. [0003] Non-volatile memory (NVM) technology is different from traditional logic technology. The combin...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L27/115H01L29/423H01L21/8247H10B69/00
Inventor 方英娇方明
Owner 浙江锋华创芯微电子有限公司